en Copyright 2015 Java http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/vec-move-17.ll#c88d3f6a [SystemZ] Reimplent SchedModel IssueWidth and WriteRes/ReadAdvance mappings.As a consequence of recent discussions(http://lists.llvm.org/pipermail/llvm-dev/2018-May/123164.html), this patchchanges the SystemZ SchedModels so that the IssueWidth is 6, which is thedecoder capacity, and NumMicroOps become the number of decoder slots neededper instruction.In addition, the SchedWrite latencies now match the MachineInstructionsdef-operand indexes, and ReadAdvances have been added on instructions withone register operand and one memory operand.Review: Ulrich Weigandhttps://reviews.llvm.org/D47008llvm-svn: 337538 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/vec-move-17.ll Fri, 20 Jul 2018 09:40:43 +0000 Jonas Paulsson <paulsson@linux.vnet.ibm.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/vec-move-17.ll#422dfbf7 [SelectionDAG] Consider endianness in scalarizeVectorStore().When handling vectors with non byte-sized elements, reverse the order of theelements in the built integer if the target is Big-Endian.SystemZ tests updated.Review: Eli Friedman, Ulrich Weigand.https://reviews.llvm.org/D42786llvm-svn: 324063 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/vec-move-17.ll Fri, 02 Feb 2018 08:48:02 +0000 Jonas Paulsson <paulsson@linux.vnet.ibm.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/vec-move-17.ll#7ad28863 [SelectionDAG] Fix codegen of vector stores with non byte-sized elements.This was completely broken, but hopefully fixed by this patch.In cases where it is needed, a vector with non byte-sized elements is storedby extracting, zero-extending, shift:ing and or:ing the elements into aninteger of the same width as the vector, which is then stored.Review: Eli Friedman, Ulrich Weigandhttps://reviews.llvm.org/D42100#inline-369520https://bugs.llvm.org/show_bug.cgi?id=35520llvm-svn: 323042 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/vec-move-17.ll Sat, 20 Jan 2018 16:05:10 +0000 Jonas Paulsson <paulsson@linux.vnet.ibm.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/vec-move-17.ll#2693c0a4 [LegalizeVectorTypes] Allow single loads and stores for more short vectorsWhen lowering a load or store for TypeWidenVector, the type legalizerwould use a single load or store if the associated integer type was legal.E.g. it would load a v4i8 as an i32 if i32 was legal.This patch extends that behavior to promoted integers as well as legal ones.If the integer type for the full vector width is TypePromoteInteger,the element type is going to be TypePromoteInteger too, and it's stillbetter to use a single promoting load or truncating store rather than Nindividual promoting loads or truncating stores. E.g. if you have a v2i8on a target where i16 is promoted to i32, it's better to load the v2i8 asan i16 rather than load both i8s individually.Original patch by Richard Sandiford.llvm-svn: 236528 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/vec-move-17.ll Tue, 05 May 2015 19:32:57 +0000 Ulrich Weigand <ulrich.weigand@de.ibm.com>