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    <title>Changes in vec-move-03.ll</title>
    <description></description>
    <language>en</language>
    <copyright>Copyright 2015</copyright>
    <generator>Java</generator><item>
        <title>cf426100 - [SystemZ] Improve emission of alignment hints.</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/vec-move-03.ll#cf426100</link>
        <description>[SystemZ] Improve emission of alignment hints.Handle multiple memoperands in lowerAlignmentHint().Review: Ulrich Weigand

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/vec-move-03.ll</description>
        <pubDate>Thu, 17 Feb 2022 01:12:06 +0000</pubDate>
        <dc:creator>Jonas Paulsson &lt;paulsson@linux.vnet.ibm.com&gt;</dc:creator>
    </item>
<item>
        <title>3641b10f - [SystemZ] Support vector load/store alignment hints</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/vec-move-03.ll#3641b10f</link>
        <description>[SystemZ] Support vector load/store alignment hintsVector load/store instructions support an optional alignment fieldthat the compiler can use to provide known alignment info to thehardware.  If the field is used (and the information is correct),the hardware may be able (on some models) to perform faster memoryaccesses than otherwise.This patch adds support for alignment hints in the assembler anddisassembler, and fills in known alignment during codegen.llvm-svn: 363806

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/vec-move-03.ll</description>
        <pubDate>Wed, 19 Jun 2019 14:20:00 +0000</pubDate>
        <dc:creator>Ulrich Weigand &lt;ulrich.weigand@de.ibm.com&gt;</dc:creator>
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<item>
        <title>2693c0a4 - [LegalizeVectorTypes] Allow single loads and stores for more short vectors</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/vec-move-03.ll#2693c0a4</link>
        <description>[LegalizeVectorTypes] Allow single loads and stores for more short vectorsWhen lowering a load or store for TypeWidenVector, the type legalizerwould use a single load or store if the associated integer type was legal.E.g. it would load a v4i8 as an i32 if i32 was legal.This patch extends that behavior to promoted integers as well as legal ones.If the integer type for the full vector width is TypePromoteInteger,the element type is going to be TypePromoteInteger too, and it&apos;s stillbetter to use a single promoting load or truncating store rather than Nindividual promoting loads or truncating stores.  E.g. if you have a v2i8on a target where i16 is promoted to i32, it&apos;s better to load the v2i8 asan i16 rather than load both i8s individually.Original patch by Richard Sandiford.llvm-svn: 236528

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/vec-move-03.ll</description>
        <pubDate>Tue, 05 May 2015 19:32:57 +0000</pubDate>
        <dc:creator>Ulrich Weigand &lt;ulrich.weigand@de.ibm.com&gt;</dc:creator>
    </item>
<item>
        <title>80b3af7a - [SystemZ] Add CodeGen support for v4f32</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/vec-move-03.ll#80b3af7a</link>
        <description>[SystemZ] Add CodeGen support for v4f32The architecture doesn&apos;t really have any native v4f32 operations exceptv4f32-&gt;v2f64 and v2f64-&gt;v4f32 conversions, with only half of the v4f32elements being used.  Even so, using vector registers for &lt;4 x float&gt;and scalarising individual operations is much better than generatingcompletely scalar code, since there&apos;s much less register pressure.It&apos;s also more efficient to do v4f32 comparisons by extending to 2v2f64s, comparing those, then packing the result.This particularly helps with llvmpipe.Based on a patch by Richard Sandiford.llvm-svn: 236523

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/vec-move-03.ll</description>
        <pubDate>Tue, 05 May 2015 19:27:45 +0000</pubDate>
        <dc:creator>Ulrich Weigand &lt;ulrich.weigand@de.ibm.com&gt;</dc:creator>
    </item>
<item>
        <title>cd808237 - [SystemZ] Add CodeGen support for v2f64</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/vec-move-03.ll#cd808237</link>
        <description>[SystemZ] Add CodeGen support for v2f64This adds ABI and CodeGen support for the v2f64 type, which is nativelysupported by z13 instructions.Based on a patch by Richard Sandiford.llvm-svn: 236522

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/vec-move-03.ll</description>
        <pubDate>Tue, 05 May 2015 19:26:48 +0000</pubDate>
        <dc:creator>Ulrich Weigand &lt;ulrich.weigand@de.ibm.com&gt;</dc:creator>
    </item>
<item>
        <title>ce4c1095 - [SystemZ] Add CodeGen support for integer vector types</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/vec-move-03.ll#ce4c1095</link>
        <description>[SystemZ] Add CodeGen support for integer vector typesThis the first of a series of patches to add CodeGen support exploitingthe instructions of the z13 vector facility.  This patch adds supportfor the native integer vector types (v16i8, v8i16, v4i32, v2i64).When the vector facility is present, we default to the new vector ABI.This is characterized by two major differences:- Vector types are passed/returned in vector registers  (except for unnamed arguments of a variable-argument list function).- Vector types are at most 8-byte aligned.The reason for the choice of 8-byte vector alignment is that the hardwareis able to efficiently load vectors at 8-byte alignment, and the ABI onlyguarantees 8-byte alignment of the stack pointer, so requiring any higheralignment for vectors would require dynamic stack re-alignment code.However, for compatibility with old code that may use vector types, when*not* using the vector facility, the old alignment rules (vector typesare naturally aligned) remain in use.These alignment rules are not only implemented at the C language level(implemented in clang), but also at the LLVM IR level.  This is doneby selecting a different DataLayout string depending on whether thevector ABI is in effect or not.Based on a patch by Richard Sandiford.llvm-svn: 236521

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/vec-move-03.ll</description>
        <pubDate>Tue, 05 May 2015 19:25:42 +0000</pubDate>
        <dc:creator>Ulrich Weigand &lt;ulrich.weigand@de.ibm.com&gt;</dc:creator>
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