Changes in vec-conv-02.ll

f43b5100 - [SystemZ] Make better use of VLDEB

Thu, 20 Dec 2018 12:59:05 +0000

[SystemZ] Make better use of VLDEBWe already have special code (DAG combine support for FP_ROUND)to recognize cases where we an use a vector version of VLEDB toperform two floating-point truncates in parallel, but equivalentsupport for VLEDB (vector floating-point extends) has beenmissing so far. This patch adds corresponding DAG combinesupport for FP_EXTEND.llvm-svn: 349746 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/vec-conv-02.ll

49506d78 - [SystemZ] Add CodeGen support for scalar f64 ops in vector registers

Tue, 05 May 2015 19:28:34 +0000

[SystemZ] Add CodeGen support for scalar f64 ops in vector registersThe z13 vector facility includes some instructions that operate only on thehigh f64 in a v2f64, effectively extending the FP register set from 16to 32 registers. It's still better to use the old instructions if theoperands happen to fit though, since the older instructions have a shorterencoding.Based on a patch by Richard Sandiford.llvm-svn: 236524 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/vec-conv-02.ll

80b3af7a - [SystemZ] Add CodeGen support for v4f32

Tue, 05 May 2015 19:27:45 +0000

[SystemZ] Add CodeGen support for v4f32The architecture doesn't really have any native v4f32 operations exceptv4f32->v2f64 and v2f64->v4f32 conversions, with only half of the v4f32elements being used. Even so, using vector registers for <4 x float>and scalarising individual operations is much better than generatingcompletely scalar code, since there's much less register pressure.It's also more efficient to do v4f32 comparisons by extending to 2v2f64s, comparing those, then packing the result.This particularly helps with llvmpipe.Based on a patch by Richard Sandiford.llvm-svn: 236523 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/vec-conv-02.ll