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    <title>Changes in fp-cmp-07.mir</title>
    <description></description>
    <language>en</language>
    <copyright>Copyright 2015</copyright>
    <generator>Java</generator><item>
        <title>fae05692 - CodeGen: Print/parse LLTs in MachineMemOperands</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/fp-cmp-07.mir#fae05692</link>
        <description>CodeGen: Print/parse LLTs in MachineMemOperandsThis will currently accept the old number of bytes syntax, and convertit to a scalar. This should be removed in the near future (I think Iconverted all of the tests already, but likely missed a few).Not sure what the exact syntax and policy should be. We can continueprinting the number of bytes for non-generic instructions to avoidtest churn and only allow non-scalar types for generic instructions.This will currently print the LLT in parentheses, but accept parsingthe existing integers and implicitly converting to scalar. Theparentheses are a bit ugly, but the parser logic seems unable to dealwithout either parentheses or some keyword to indicate the start of atype.

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/fp-cmp-07.mir</description>
        <pubDate>Thu, 20 May 2021 02:25:51 +0000</pubDate>
        <dc:creator>Matt Arsenault &lt;Matthew.Arsenault@amd.com&gt;</dc:creator>
    </item>
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        <title>8e42f6dd - [SystemZ] Model floating-point control register</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/fp-cmp-07.mir#8e42f6dd</link>
        <description>[SystemZ] Model floating-point control registerThis adds the FPC (floating-point control register) as a reservedphysical register and models its use by SystemZ instructions.Note that only the current rounding modes and the IEEE exceptionmasks are modeled.  *Changes* of the FPC due to exceptions (inparticular the IEEE exception flags and the DXC) are not modeled.At this point, this patch is mostly NFC, but it will preventscheduling of floating-point instructions across SPFC/LFPC etc.llvm-svn: 360570

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/fp-cmp-07.mir</description>
        <pubDate>Mon, 13 May 2019 09:47:26 +0000</pubDate>
        <dc:creator>Ulrich Weigand &lt;ulrich.weigand@de.ibm.com&gt;</dc:creator>
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<item>
        <title>43e94b15 - Followup on Proposal to move MIR physical register namespace to &apos;$&apos; sigil.</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/fp-cmp-07.mir#43e94b15</link>
        <description>Followup on Proposal to move MIR physical register namespace to &apos;$&apos; sigil.Discussed here:http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.htmlIn preparation for adding support for named vregs we are changing the sigil forphysical registers in MIR to &apos;$&apos; from &apos;%&apos;. This will prevent name clashes ofnamed physical register with named vregs.llvm-svn: 323922

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/fp-cmp-07.mir</description>
        <pubDate>Wed, 31 Jan 2018 22:04:26 +0000</pubDate>
        <dc:creator>Puyan Lotfi &lt;puyan@puyan.org&gt;</dc:creator>
    </item>
<item>
        <title>fe6c9cbb - [MIR] Repurposing &apos;$&apos; sigil used by external symbols. Replacing with &apos;&amp;&apos;.</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/fp-cmp-07.mir#fe6c9cbb</link>
        <description>[MIR] Repurposing &apos;$&apos; sigil used by external symbols. Replacing with &apos;&amp;&apos;.Planning to add support for named vregs. This puts is in a conundrum sincephysregs are named as well. To rectify this we need to use a sigil other than&apos;%&apos; for physregs in MIR. We&apos;ve settled on using &apos;$&apos; for physregs but first wemust repurpose it from external symbols using it, which is what this commit isall about. We think &apos;&amp;&apos; will have familiar semantics for C/C++ users.llvm-svn: 322146

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/fp-cmp-07.mir</description>
        <pubDate>Wed, 10 Jan 2018 00:56:48 +0000</pubDate>
        <dc:creator>Puyan Lotfi &lt;puyan@puyan.org&gt;</dc:creator>
    </item>
<item>
        <title>c71cced0 - [CodeGen] Always use `printReg` to print registers in both MIR and debug</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/fp-cmp-07.mir#c71cced0</link>
        <description>[CodeGen] Always use `printReg` to print registers in both MIR and debugoutputAs part of the unification of the debug format and the MIR format,always use `printReg` to print all kinds of registers.Updated the tests using &apos;_&apos; instead of &apos;%noreg&apos; until we decide whichone we want to be the default one.Differential Revision: https://reviews.llvm.org/D40421llvm-svn: 319445

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/fp-cmp-07.mir</description>
        <pubDate>Thu, 30 Nov 2017 16:12:24 +0000</pubDate>
        <dc:creator>Francis Visoiu Mistrih &lt;francisvm@yahoo.com&gt;</dc:creator>
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<item>
        <title>b0e8a2e6 - [SystemZ]  Improve optimizeCompareZero()</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/fp-cmp-07.mir#b0e8a2e6</link>
        <description>[SystemZ]  Improve optimizeCompareZero()More conversions to load-and-test can be made with this patch by adding aforward search in optimizeCompareZero().Review: Ulrich Weigandhttps://reviews.llvm.org/D38076llvm-svn: 313877

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/fp-cmp-07.mir</description>
        <pubDate>Thu, 21 Sep 2017 13:52:24 +0000</pubDate>
        <dc:creator>Jonas Paulsson &lt;paulsson@linux.vnet.ibm.com&gt;</dc:creator>
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