en Copyright 2015 Java http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/stack-store-check.ll#8def89b5 [RISCV] Set CostPerUse to 1 iff RVC is enabledAfter D86836, we can define multiple cost values fordifferent cost models. So here we set CostPerUse to1 iff RVC is enabled to avoid potential impact on RA.Reviewed By: craig.topperDifferential Revision: https://reviews.llvm.org/D117741 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/stack-store-check.ll Fri, 21 Jan 2022 05:54:09 +0000 wangpc <pc.wang@linux.alibaba.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/stack-store-check.ll#137d3474 [RISCV] Reverse the order of loading/storing callee-saved registers.Currently, we restore the return address register as the last restoringinstruction in the epilog. The next instruction is `ret` usually. It isa use of return address register. In some microarchitectures, there isload-to-use data hazard. To avoid the load-to-use data hazard, we couldseparate the load instruction from its use as far as possible. In thispatch, we reverse the order of restoring callee-saved registers toincrease the distance of `load ra` and `ret` in the epilog.Differential Revision: https://reviews.llvm.org/D113967 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/stack-store-check.ll Tue, 16 Nov 2021 08:01:37 +0000 Hsiangkai Wang <kai.wang@sifive.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/stack-store-check.ll#4a36e96c RegAllocGreedy: Account for reserved registers in num regs heuristicThis simple heuristic uses the estimated live range length combinedwith the number of registers in the class to switch which heuristic touse. This was taking the raw number of registers in the class, eventhough not all of them may be available. AMDGPU heavily relies ondynamically reserved numbers of registers based on user attributes tosatisfy occupancy constraints, so the raw number is highly misleading.There are still a few problems here. In the original testcase thatmade me notice this, the live range size is incorrect after thescheduler rearranges instructions, since the instructions don't havethe original InstrDist offsets. Additionally, I think it would be moreappropriate to use the number of disjointly allocatable registers inthe class. For the AMDGPU register tuples, there are a large number ofregisters in each tuple class, but only a small fraction can actuallybe allocated at the same time since they all overlap with eachother. It seems we do not have a query that corresponds to the numberof independently allocatable registers. Relatedly, I'm still debuggingsome allocation failures where overlapping tuples seem to not behandled correctly.The test changes are mostly noise. There are a handful of x86 teststhat look like regressions with an additional spill, and a handfulthat now avoid a spill. The worst looking regression is likelytest/Thumb2/mve-vld4.ll which introduces a few additionalspills. test/CodeGen/AMDGPU/soft-clause-exceeds-register-budget.llshows a massive improvement by completely eliminating a large numberof spills inside a loop. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/stack-store-check.ll Sat, 21 Aug 2021 18:54:51 +0000 Matt Arsenault <Matthew.Arsenault@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/stack-store-check.ll#e28b6a60 [RISCV][NFC] Regenerate RISCV CodeGen testsRegenerated using:./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.llThis has added comments to spill-related instructions and added @plt tosome symbols.Differential Revision: https://reviews.llvm.org/D92841 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/stack-store-check.ll Wed, 09 Dec 2020 19:41:19 +0000 Michael Munday <mike.munday@lowrisc.org> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/stack-store-check.ll#0cbdd2a8 [RISCV] Fix isStoreToStackSlotBecause of the layout of stores (that don't have a destination operand)this check is exactly the same as the one inRISCVInstrInfo::isLoadFromStackSlot.Differential Revision: https://reviews.llvm.org/D81805 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/stack-store-check.ll Tue, 14 Jul 2020 07:26:01 +0000 Roger Ferrer Ibanez <roger.ferrer@bsc.es> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/stack-store-check.ll#c1d021e2 [NFC][RISCV] Test for D81805New test to show the changes after D81805 is committed.Differential Revision: https://reviews.llvm.org/D83750 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/stack-store-check.ll Tue, 14 Jul 2020 07:18:07 +0000 Roger Ferrer Ibanez <roger.ferrer@bsc.es>