Changes in vtruncs-sdnode.ll

9b0f227d - [TableGen][RISCV] Add InstAliases with zero_reg to cover unmasked vnot.v, vncvt.x.x.w, vneg.v, etc.

Tue, 22 Mar 2022 16:53:39 +0000

[TableGen][RISCV] Add InstAliases with zero_reg to cover unmasked vnot.v, vncvt.x.x.w, vneg.v, etc.The mask being NoRegister prevented the existing aliases from matchingsince NoRegister isn't in the VMV0 register class.To workaround this I've added new aliases that look for zero_reg.I had to motify tablegen to generate matching code for zero_reg.And as a consequence, I had to change the EmitPriority for an ARMalias that used zero_reg that started printing.Reviewed By: frasercrmckDifferential Revision: https://reviews.llvm.org/D121496 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode.ll

b3bec6e4 - [RISCV] Use vnsrl.wx with x0 instead of vnsrl.vi for truncate.

Thu, 27 Jan 2022 02:20:04 +0000

[RISCV] Use vnsrl.wx with x0 instead of vnsrl.vi for truncate.This matches what the spec uses for the vncvt.x.x.w assemblypseudoinstruction.Reviewed By: kito-chengDifferential Revision: https://reviews.llvm.org/D118295 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode.ll

3cf15af2 - [RISCV] Remove experimental prefix from rvv-related extensions.

Fri, 21 Jan 2022 08:39:23 +0000

[RISCV] Remove experimental prefix from rvv-related extensions.Extensions affected: +v, +zve*, +zvl*Reviewed By: craig.topperDifferential Revision: https://reviews.llvm.org/D117860 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode.ll

0a9b8296 - [RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.

Fri, 02 Jul 2021 01:25:50 +0000

[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.If we know the source operand of COPY is defined by a vector instructionwith tail agnostic and the same LMUL and there is no vsetvli betweenCOPY and the define instruction to change the vl and vtype, we could usevmv.v.v or vmv.v.i to copy vector registers to get better performance thanthe whole vector register move instructions.If the source of COPY is from vmv.v.i, we could use vmv.v.i for theCOPY.This patch only considers all these instructions within one basic block.Case 1:```bb.0: ... VSETVLI # The first VSETVLI before COPY and VOP. ... # Use this VSETVLI to check LMUL and tail agnostic. ... vy = VOP va, vb # Define vy. ... # There is no vsetvli between VOP and COPY. vx = COPY vy```Case 2:```bb.0: ... VSETVLI # The first VSETVLI before VOP. ... # Use this VSETVLI to check LMUL and tail agnostic. ... vy = VOP va, vb # Define vy. ... # There is no vsetvli to change vl between VOP and COPY. ... VSETVLI # The first VSETVLI before COPY. ... # This VSETVLI does not change vl and vtype. ... vx = COPY vy```Co-Authored-by: Zakk Chen Co-Authored-by: Kito Cheng Differential Revision: https://reviews.llvm.org/D103510 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode.ll

ce7b8343 - [RISCV] Merge vector tests for rv32 and rv64 into a single test file

Thu, 21 Oct 2021 17:22:02 +0000

[RISCV] Merge vector tests for rv32 and rv64 into a single test fileThese tests have nearly identical content the only difference isthat the rv64 test has a signext attribute on some parameters.That attribute should be harmless on rv32.Merge them into a single test file with 2 RUN lines.Differential Revision: https://reviews.llvm.org/D112242 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode.ll