en Copyright 2015 Java http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll#c06d0b4d [RISCV] Add ADDI instr for computing FrameIndex addressRVV doesn't have immediate field for memory addressing. Currentlywe build MachineInstructions in PEI to computing stack offset forRVV load store instructions. These instructions were added too late tocan be optimized by CSE, LICM... passes.This patch makes FrameIndex SDNodes can't be matched in RVV Load Storeinstruction selection patterns. So that the FrameIndex SDNodes would beselected as `ADDI GPR, targetframeindex`.There are 2 advantages for such change:1. Stack objects address computing can be optimized by machine functionpasses.2. Since the ADDI instruction's destination register can be used as atemp register, we can save an emergency spill slot.Differential Revision: https://reviews.llvm.org/D128187 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll Sun, 19 Jun 2022 12:01:25 +0000 luxufan <luxufan@iscas.ac.cn> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll#e9ceeedf [RISCV][3/3] Switch undef -> poison in scalable-vector RVV tests List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll Tue, 01 Feb 2022 10:54:39 +0000 Fraser Cormack <fraser@codeplay.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll#3cf15af2 [RISCV] Remove experimental prefix from rvv-related extensions.Extensions affected: +v, +zve*, +zvl*Reviewed By: craig.topperDifferential Revision: https://reviews.llvm.org/D117860 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll Fri, 21 Jan 2022 08:39:23 +0000 eopXD <eop.chen@sifive.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll#facff468 [RISCV] Reorder the vector register allocation order.GPR uses argument registers as the first group of registers to allocate.This patch uses vector argument registers, v8 to v23, as the first groupto allocate.Differential Revision: https://reviews.llvm.org/D111304 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll Thu, 07 Oct 2021 11:30:33 +0000 Hsiangkai Wang <kai.wang@sifive.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll#172487fe [RISCV] Add support for vector saturating add/sub operationsThis patch adds support for lowering the saturating vector add/subintrinsics to RVV instructions, for both fixed-length andscalable-vector forms alike.Note that some of the DAG combines are still not triggering for thescalable-vector tests. These require a bit more work in the DAGCombineritself.Reviewed By: craig.topperDifferential Revision: https://reviews.llvm.org/D106651 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll Fri, 23 Jul 2021 10:10:04 +0000 Fraser Cormack <fraser@codeplay.com>