Changes in vrem-sdnode.ll

c06d0b4d - [RISCV] Add ADDI instr for computing FrameIndex address

Sun, 19 Jun 2022 12:01:25 +0000

[RISCV] Add ADDI instr for computing FrameIndex addressRVV doesn't have immediate field for memory addressing. Currentlywe build MachineInstructions in PEI to computing stack offset forRVV load store instructions. These instructions were added too late tocan be optimized by CSE, LICM... passes.This patch makes FrameIndex SDNodes can't be matched in RVV Load Storeinstruction selection patterns. So that the FrameIndex SDNodes would beselected as `ADDI GPR, targetframeindex`.There are 2 advantages for such change:1. Stack objects address computing can be optimized by machine functionpasses.2. Since the ADDI instruction's destination register can be used as atemp register, we can save an emergency spill slot.Differential Revision: https://reviews.llvm.org/D128187 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll

e9ceeedf - [RISCV][3/3] Switch undef -> poison in scalable-vector RVV tests

Tue, 01 Feb 2022 10:54:39 +0000

[RISCV][3/3] Switch undef -> poison in scalable-vector RVV tests List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll

b089e407 - [RISCV] Don't allow i64 vector div by constant to use mulh with Zve64x

Sat, 22 Jan 2022 08:46:36 +0000

[RISCV] Don't allow i64 vector div by constant to use mulh with Zve64xEEW=64 of mulh and its vairants requires V extension.Authored by: Craig Topper @craig.topperReviewed By: craig.topperDifferential Revision: https://reviews.llvm.org/D117947 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll

3cf15af2 - [RISCV] Remove experimental prefix from rvv-related extensions.

Fri, 21 Jan 2022 08:39:23 +0000

[RISCV] Remove experimental prefix from rvv-related extensions.Extensions affected: +v, +zve*, +zvl*Reviewed By: craig.topperDifferential Revision: https://reviews.llvm.org/D117860 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll

41454ab2 - [RISCV] Use constant pool for large integers

Fri, 31 Dec 2021 06:01:53 +0000

[RISCV] Use constant pool for large integersFor large integers (for example, magic numbers generated byTargetLowering::BuildSDIV when dividing by constant), we mayneed about 4~8 instructions to build them.In the same time, it just takes two instructions to loadconstants (with extra cycles to access memory), so it may beprofitable to put these integers into constant pool.Reviewed By: asb, craig.topperDifferential Revision: https://reviews.llvm.org/D114950 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll

af0ecfcc - [RISCV] Generate pseudo instruction li

Mon, 22 Nov 2021 06:01:37 +0000

[RISCV] Generate pseudo instruction liAdd an alias of `addi [x], zero, imm` to generate pseudoinstruction li, which makes assembly mush more readable.For existed tests, users can update them by running script`llvm/utils/update_llc_test_checks.py`.Reviewed By: asbDifferential Revision: https://reviews.llvm.org/D112692 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll

ce7b8343 - [RISCV] Merge vector tests for rv32 and rv64 into a single test file

Thu, 21 Oct 2021 17:22:02 +0000

[RISCV] Merge vector tests for rv32 and rv64 into a single test fileThese tests have nearly identical content the only difference isthat the rv64 test has a signext attribute on some parameters.That attribute should be harmless on rv32.Merge them into a single test file with 2 RUN lines.Differential Revision: https://reviews.llvm.org/D112242 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll