Changes in vpgather-sdnode.ll

d1a5669f - [RISCV] Disable subregister liveness by default

Wed, 13 Jul 2022 14:48:40 +0000

[RISCV] Disable subregister liveness by defaultWe previously enabled subregister liveness by default when compilingwith RVV. This has been shown to cause miscompilations where RVVregister operand constraints are not met. A test was added for this inD129639 which explains the issue in more detail.Until this issue is fixed in some way, we should not be enablingsubregister liveness unless the user asks for it.Reviewed By: craig.topper, rogfer01, kito-chengDifferential Revision: https://reviews.llvm.org/D129646 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll

59cde213 - Recommit "[RISCV] Enable subregister liveness tracking for RVV."

Tue, 21 Jun 2022 03:20:00 +0000

Recommit "[RISCV] Enable subregister liveness tracking for RVV."The failure that caused the previous revert has been fixedby https://reviews.llvm.org/D126048Original commit message:RVV makes heavy use of subregisters due to LMUL>1 and segmentload/store tuples. Enabling subregister liveness tracking improves the qualityof the register allocation.I've added a command line that can be used to turn it off if it causes compiletime or functional issues. I used the command line to keep the old behaviorfor one interesting test case that was testing register allocation.Reviewed By: kito-chengDifferential Revision: https://reviews.llvm.org/D128016 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll

a2918976 - Revert "[RISCV] Enable subregister liveness tracking for RVV."

Fri, 13 May 2022 17:57:35 +0000

Revert "[RISCV] Enable subregister liveness tracking for RVV."This reverts most of ed242b54c9c2aa84a47f66af5b8497d93646b68dI'm seeing failures in our intrinsic testing on qemu that seemrelated to this. Reverting while I investigate.I've left the command line option in place for directed testing.It defaults to off. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll

ed242b54 - [RISCV] Enable subregister liveness tracking for RVV.

Wed, 11 May 2022 19:49:01 +0000

[RISCV] Enable subregister liveness tracking for RVV.RVV makes heavy use of subregisters due to LMUL>1 and segmentload/store tuples. Enabling subregister liveness tracking improves the qualityof the register allocation.I've added a command line that can be used to turn it off if it causes compiletime or functional issues. I used the command line to keep the old behaviorfor one interesting test case that was testing register allocation.Reviewed By: frasercrmckDifferential Revision: https://reviews.llvm.org/D125108 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll

9b0f227d - [TableGen][RISCV] Add InstAliases with zero_reg to cover unmasked vnot.v, vncvt.x.x.w, vneg.v, etc.

Tue, 22 Mar 2022 16:53:39 +0000

[TableGen][RISCV] Add InstAliases with zero_reg to cover unmasked vnot.v, vncvt.x.x.w, vneg.v, etc.The mask being NoRegister prevented the existing aliases from matchingsince NoRegister isn't in the VMV0 register class.To workaround this I've added new aliases that look for zero_reg.I had to motify tablegen to generate matching code for zero_reg.And as a consequence, I had to change the EmitPriority for an ARMalias that used zero_reg that started printing.Reviewed By: frasercrmckDifferential Revision: https://reviews.llvm.org/D121496 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll

bbd2ecf9 - [RISCV] Add +experimental-zvfh extension to cover half types in vectors.

Thu, 17 Mar 2022 16:44:43 +0000

[RISCV] Add +experimental-zvfh extension to cover half types in vectors.Currently we allow half types in vectors if the scalar Zfh extensionis enabled. This behavior is not inline with the vector spec. For f32and f64 types, the Zve32f, Zve64f, Zve64d, and V explicitly controlthe availablity of floating point types in vectors.In order to make our compiler compliant, we either need to remove all supportfor half in vectors or we need an extension to control it.Draft spec here https://github.com/riscv/riscv-v-spec/pull/780Reviewed By: kito-chengDifferential Revision: https://reviews.llvm.org/D121345 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll

414f21ed - [RISCV][1/3] Switch undef -> poison in VP RVV tests

Tue, 01 Feb 2022 10:51:01 +0000

[RISCV][1/3] Switch undef -> poison in VP RVV testsInspired by a recent Discourse post on undef vs. poison usage, thisseries of patches should reduce the number of undefs in LLVM tests byaround 10%.Only undef vector operands to insertelement/shufflevector have beenhandled, which are by far the most common we've got.The switchover is split into 3 fairly arbitrary clusters to make itslightly more manageable: vector predication, fixed-length vectors,scalable vectors. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll

ea05ee90 - [RISCV] Preserve VL when truncating i64 gather/scatter indices on RV32.

Fri, 28 Jan 2022 17:21:52 +0000

[RISCV] Preserve VL when truncating i64 gather/scatter indices on RV32.We were creating a truncate with the default for the type, but forVP intrinsics we have a VL that we should use.Reviewed By: frasercrmckDifferential Revision: https://reviews.llvm.org/D118406 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll

b3bec6e4 - [RISCV] Use vnsrl.wx with x0 instead of vnsrl.vi for truncate.

Thu, 27 Jan 2022 02:20:04 +0000

[RISCV] Use vnsrl.wx with x0 instead of vnsrl.vi for truncate.This matches what the spec uses for the vncvt.x.x.w assemblypseudoinstruction.Reviewed By: kito-chengDifferential Revision: https://reviews.llvm.org/D118295 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll

19d3dc6e - [VP] Update CodeGen/RISCV/rvv/vpgather-sdnode.ll test

Tue, 25 Jan 2022 10:34:58 +0000

[VP] Update CodeGen/RISCV/rvv/vpgather-sdnode.ll test List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll

2233befa - [LegalizeTypes][VP] Add splitting support for vp.gather and vp.scatter

Tue, 25 Jan 2022 10:05:50 +0000

[LegalizeTypes][VP] Add splitting support for vp.gather and vp.scatterSplit these nodes in a similar way as their masked versions.Reviewed By: frasercrmck, craig.topperDifferential Revision: https://reviews.llvm.org/D117760 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll

3cf15af2 - [RISCV] Remove experimental prefix from rvv-related extensions.

Fri, 21 Jan 2022 08:39:23 +0000

[RISCV] Remove experimental prefix from rvv-related extensions.Extensions affected: +v, +zve*, +zvl*Reviewed By: craig.topperDifferential Revision: https://reviews.llvm.org/D117860 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll

c10c7488 - [LegalizeTypes][VP] Add widening support for vp.gather and vp.scatter

Thu, 20 Jan 2022 08:13:00 +0000

[LegalizeTypes][VP] Add widening support for vp.gather and vp.scatterReviewed By: craig.topperDifferential Revision: https://reviews.llvm.org/D117557 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll

a0a76fee - [RISCV] update zfh and zfhmin extention to v1.0

Sat, 15 Jan 2022 01:11:58 +0000

[RISCV] update zfh and zfhmin extention to v1.0`zfh` and `zfhmin` have been ratified, with version 1.0.Reviewed By: craig.topperDifferential Revision: https://reviews.llvm.org/D117098 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll

6b8362eb - [RISCV] Disable EEW=64 for index values when XLEN=32.

Thu, 22 Jul 2021 03:40:31 +0000

[RISCV] Disable EEW=64 for index values when XLEN=32.Disable EEW=64 for vector index load/store when XLEN=32.Differential Revision: https://reviews.llvm.org/D106518 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll

0a9b8296 - [RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.

Fri, 02 Jul 2021 01:25:50 +0000

[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.If we know the source operand of COPY is defined by a vector instructionwith tail agnostic and the same LMUL and there is no vsetvli betweenCOPY and the define instruction to change the vl and vtype, we could usevmv.v.v or vmv.v.i to copy vector registers to get better performance thanthe whole vector register move instructions.If the source of COPY is from vmv.v.i, we could use vmv.v.i for theCOPY.This patch only considers all these instructions within one basic block.Case 1:```bb.0: ... VSETVLI # The first VSETVLI before COPY and VOP. ... # Use this VSETVLI to check LMUL and tail agnostic. ... vy = VOP va, vb # Define vy. ... # There is no vsetvli between VOP and COPY. vx = COPY vy```Case 2:```bb.0: ... VSETVLI # The first VSETVLI before VOP. ... # Use this VSETVLI to check LMUL and tail agnostic. ... vy = VOP va, vb # Define vy. ... # There is no vsetvli to change vl between VOP and COPY. ... VSETVLI # The first VSETVLI before COPY. ... # This VSETVLI does not change vl and vtype. ... vx = COPY vy```Co-Authored-by: Zakk Chen Co-Authored-by: Kito Cheng Differential Revision: https://reviews.llvm.org/D103510 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll

facff468 - [RISCV] Reorder the vector register allocation order.

Thu, 07 Oct 2021 11:30:33 +0000

[RISCV] Reorder the vector register allocation order.GPR uses argument registers as the first group of registers to allocate.This patch uses vector argument registers, v8 to v23, as the first groupto allocate.Differential Revision: https://reviews.llvm.org/D111304 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll

f4dee8cb - [RISCV][VP] Custom lower VP_SCATTER and VP_GATHER

Tue, 31 Aug 2021 11:43:12 +0000

[RISCV][VP] Custom lower VP_SCATTER and VP_GATHERThis patch adds support for the `VP_SCATTER` and `VP_GATHER` nodes bylowering them to RVV's `vsox`/`vlux` instructions, respectively. Thisprocess is almost identical to the existing `MSCATTER`/`MGATHER` support.One extra change was made to `SelectionDAGLegalize` so that`VP_SCATTER`'s operation action is derived from its stored "value"operand rather than its return type (which is always the chain).Reviewed By: craig.topper, rogfer01Differential Revision: https://reviews.llvm.org/D108987 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll