en Copyright 2015 Java http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll#62dd3674 [RISCV] Supplement SDNode patterns for vfwmul/vfwadd/vfwsubReviewed By: jacquesguanDifferential Revision: https://reviews.llvm.org/D122720 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll Thu, 31 Mar 2022 01:51:06 +0000 Lian Wang <Lian.Wang@streamcomputing.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll#bbd2ecf9 [RISCV] Add +experimental-zvfh extension to cover half types in vectors.Currently we allow half types in vectors if the scalar Zfh extensionis enabled. This behavior is not inline with the vector spec. For f32and f64 types, the Zve32f, Zve64f, Zve64d, and V explicitly controlthe availablity of floating point types in vectors.In order to make our compiler compliant, we either need to remove all supportfor half in vectors or we need an extension to control it.Draft spec here https://github.com/riscv/riscv-v-spec/pull/780Reviewed By: kito-chengDifferential Revision: https://reviews.llvm.org/D121345 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll Thu, 17 Mar 2022 16:44:43 +0000 Craig Topper <craig.topper@sifive.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll#e9ceeedf [RISCV][3/3] Switch undef -> poison in scalable-vector RVV tests List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll Tue, 01 Feb 2022 10:54:39 +0000 Fraser Cormack <fraser@codeplay.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll#3cf15af2 [RISCV] Remove experimental prefix from rvv-related extensions.Extensions affected: +v, +zve*, +zvl*Reviewed By: craig.topperDifferential Revision: https://reviews.llvm.org/D117860 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll Fri, 21 Jan 2022 08:39:23 +0000 eopXD <eop.chen@sifive.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll#c29d6c41 [RISCV] Add patterns for vector widening floating-point add/subtract instructionsAdd patterns for Vector Widening Floating-Point Add/Subtract InstructionsDifferential Revision: https://reviews.llvm.org/D117466 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll Mon, 17 Jan 2022 12:08:36 +0000 jacquesguan <Jianjian.Guan@streamcomputing.com>