en Copyright 2015 Java http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll#bbd2ecf9 [RISCV] Add +experimental-zvfh extension to cover half types in vectors.Currently we allow half types in vectors if the scalar Zfh extensionis enabled. This behavior is not inline with the vector spec. For f32and f64 types, the Zve32f, Zve64f, Zve64d, and V explicitly controlthe availablity of floating point types in vectors.In order to make our compiler compliant, we either need to remove all supportfor half in vectors or we need an extension to control it.Draft spec here https://github.com/riscv/riscv-v-spec/pull/780Reviewed By: kito-chengDifferential Revision: https://reviews.llvm.org/D121345 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll Thu, 17 Mar 2022 16:44:43 +0000 Craig Topper <craig.topper@sifive.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll#e9ceeedf [RISCV][3/3] Switch undef -> poison in scalable-vector RVV tests List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll Tue, 01 Feb 2022 10:54:39 +0000 Fraser Cormack <fraser@codeplay.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll#3cf15af2 [RISCV] Remove experimental prefix from rvv-related extensions.Extensions affected: +v, +zve*, +zvl*Reviewed By: craig.topperDifferential Revision: https://reviews.llvm.org/D117860 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll Fri, 21 Jan 2022 08:39:23 +0000 eopXD <eop.chen@sifive.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll#a0a76fee [RISCV] update zfh and zfhmin extention to v1.0`zfh` and `zfhmin` have been ratified, with version 1.0.Reviewed By: craig.topperDifferential Revision: https://reviews.llvm.org/D117098 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll Sat, 15 Jan 2022 01:11:58 +0000 Shao-Ce SUN <shaoce@nj.iscas.ac.cn> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll#242ddd50 [RISCV][NFC] Add a single space after comma for VTypeIn most of cases, it has a single space after comma in assembly operands.Reviewed By: craig.topperDifferential Revision: https://reviews.llvm.org/D103790 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll Tue, 08 Jun 2021 07:40:56 +0000 Jim Lin <jim@andestech.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll#83b8f8da [RISCV] Custom lower vector F(MIN|MAX)NUM to vf(min|max)This patch adds support for both scalable- and fixed-length vector codelowering of the llvm.minnum and llvm.maxnum intrinsics to the equivalentRVV instructions.Reviewed By: craig.topperDifferential Revision: https://reviews.llvm.org/D101035 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll Thu, 22 Apr 2021 08:55:27 +0000 Fraser Cormack <fraser@codeplay.com>