en Copyright 2015 Java http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll#9b0f227d [TableGen][RISCV] Add InstAliases with zero_reg to cover unmasked vnot.v, vncvt.x.x.w, vneg.v, etc.The mask being NoRegister prevented the existing aliases from matchingsince NoRegister isn't in the VMV0 register class.To workaround this I've added new aliases that look for zero_reg.I had to motify tablegen to generate matching code for zero_reg.And as a consequence, I had to change the EmitPriority for an ARMalias that used zero_reg that started printing.Reviewed By: frasercrmckDifferential Revision: https://reviews.llvm.org/D121496 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll Tue, 22 Mar 2022 16:53:39 +0000 Craig Topper <craig.topper@sifive.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll#bbd2ecf9 [RISCV] Add +experimental-zvfh extension to cover half types in vectors.Currently we allow half types in vectors if the scalar Zfh extensionis enabled. This behavior is not inline with the vector spec. For f32and f64 types, the Zve32f, Zve64f, Zve64d, and V explicitly controlthe availablity of floating point types in vectors.In order to make our compiler compliant, we either need to remove all supportfor half in vectors or we need an extension to control it.Draft spec here https://github.com/riscv/riscv-v-spec/pull/780Reviewed By: kito-chengDifferential Revision: https://reviews.llvm.org/D121345 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll Thu, 17 Mar 2022 16:44:43 +0000 Craig Topper <craig.topper@sifive.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll#3cf15af2 [RISCV] Remove experimental prefix from rvv-related extensions.Extensions affected: +v, +zve*, +zvl*Reviewed By: craig.topperDifferential Revision: https://reviews.llvm.org/D117860 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll Fri, 21 Jan 2022 08:39:23 +0000 eopXD <eop.chen@sifive.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll#a0a76fee [RISCV] update zfh and zfhmin extention to v1.0`zfh` and `zfhmin` have been ratified, with version 1.0.Reviewed By: craig.topperDifferential Revision: https://reviews.llvm.org/D117098 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll Sat, 15 Jan 2022 01:11:58 +0000 Shao-Ce SUN <shaoce@nj.iscas.ac.cn> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll#242ddd50 [RISCV][NFC] Add a single space after comma for VTypeIn most of cases, it has a single space after comma in assembly operands.Reviewed By: craig.topperDifferential Revision: https://reviews.llvm.org/D103790 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll Tue, 08 Jun 2021 07:40:56 +0000 Jim Lin <jim@andestech.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll#b8701990 [RISCV] Add patterns for scalable-vector fabs & fcopysignThe patterns mostly follow the scalar counterparts, save for some extraoptimizations to match the vector/scalar forms.The patch adds a DAGCombine for ISD::FCOPYSIGN to try and reorderISD::FNEG around any ISD::FP_EXTEND or ISD::FP_TRUNC of the secondoperand. This helps us achieve better codegen to match vfsgnjn.Reviewed By: craig.topperDifferential Revision: https://reviews.llvm.org/D96028 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll Thu, 04 Feb 2021 12:07:59 +0000 Fraser Cormack <fraser@codeplay.com>