en Copyright 2015 Java http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll#e60eb705 recommit "[DAGCombiner] Teach scalarizeBinOpOfSplats handle scalable splat."With fix for AArch64 and Hexgon test cases. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll Thu, 07 Jul 2022 08:48:55 +0000 jacquesguan <Jianjian.Guan@streamcomputing.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll#69b284aa Revert "[DAGCombiner] Teach scalarizeBinOpOfSplats handle scalable splat."This reverts commit 58dfaaaace4ea75ab3588a6e738f2cf58ebf77c2.Massive AARCH test failures in buildbot. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll Tue, 19 Jul 2022 06:26:31 +0000 Max Kazantsev <mkazantsev@azul.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll#58dfaaaa [DAGCombiner] Teach scalarizeBinOpOfSplats handle scalable splat.This revision supports to scalarize a binary operation of two scalable splat vectors.Reviewed By: RKSimonDifferential Revision: https://reviews.llvm.org/D122791 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll Thu, 07 Jul 2022 08:48:55 +0000 jacquesguan <Jianjian.Guan@streamcomputing.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll#3fcaea17 [RISCV][test] Precommit test for D122791.Differential Revision: https://reviews.llvm.org/D123362 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll Thu, 07 Jul 2022 08:57:59 +0000 jacquesguan <Jianjian.Guan@streamcomputing.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll#c06d0b4d [RISCV] Add ADDI instr for computing FrameIndex addressRVV doesn't have immediate field for memory addressing. Currentlywe build MachineInstructions in PEI to computing stack offset forRVV load store instructions. These instructions were added too late tocan be optimized by CSE, LICM... passes.This patch makes FrameIndex SDNodes can't be matched in RVV Load Storeinstruction selection patterns. So that the FrameIndex SDNodes would beselected as `ADDI GPR, targetframeindex`.There are 2 advantages for such change:1. Stack objects address computing can be optimized by machine functionpasses.2. Since the ADDI instruction's destination register can be used as atemp register, we can save an emergency spill slot.Differential Revision: https://reviews.llvm.org/D128187 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll Sun, 19 Jun 2022 12:01:25 +0000 luxufan <luxufan@iscas.ac.cn> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll#e9ceeedf [RISCV][3/3] Switch undef -> poison in scalable-vector RVV tests List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll Tue, 01 Feb 2022 10:54:39 +0000 Fraser Cormack <fraser@codeplay.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll#3cf15af2 [RISCV] Remove experimental prefix from rvv-related extensions.Extensions affected: +v, +zve*, +zvl*Reviewed By: craig.topperDifferential Revision: https://reviews.llvm.org/D117860 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll Fri, 21 Jan 2022 08:39:23 +0000 eopXD <eop.chen@sifive.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll#ce7b8343 [RISCV] Merge vector tests for rv32 and rv64 into a single test fileThese tests have nearly identical content the only difference isthat the rv64 test has a signext attribute on some parameters.That attribute should be harmless on rv32.Merge them into a single test file with 2 RUN lines.Differential Revision: https://reviews.llvm.org/D112242 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll Thu, 21 Oct 2021 17:22:02 +0000 Craig Topper <craig.topper@sifive.com>