en Copyright 2015 Java http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/stepvector.ll#c06d0b4d [RISCV] Add ADDI instr for computing FrameIndex addressRVV doesn't have immediate field for memory addressing. Currentlywe build MachineInstructions in PEI to computing stack offset forRVV load store instructions. These instructions were added too late tocan be optimized by CSE, LICM... passes.This patch makes FrameIndex SDNodes can't be matched in RVV Load Storeinstruction selection patterns. So that the FrameIndex SDNodes would beselected as `ADDI GPR, targetframeindex`.There are 2 advantages for such change:1. Stack objects address computing can be optimized by machine functionpasses.2. Since the ADDI instruction's destination register can be used as atemp register, we can save an emergency spill slot.Differential Revision: https://reviews.llvm.org/D128187 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/stepvector.ll Sun, 19 Jun 2022 12:01:25 +0000 luxufan <luxufan@iscas.ac.cn> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/stepvector.ll#16215eb9 [LegalizeTypes][RISCV][NFC] Modify assert in PromoteIntRes_STEP_VECTOR and add some tests for RISCVReviewed By: david-armDifferential Revision: https://reviews.llvm.org/D127939 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/stepvector.ll Thu, 16 Jun 2022 03:31:48 +0000 Lian Wang <Lian.Wang@streamcomputing.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/stepvector.ll#362a02da [RISCV][test] Add widen STEP_VECTOR tests.Reviewed By: reamesDifferential Revision: https://reviews.llvm.org/D127371 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/stepvector.ll Thu, 09 Jun 2022 07:34:54 +0000 Lian Wang <Lian.Wang@streamcomputing.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/stepvector.ll#3cf15af2 [RISCV] Remove experimental prefix from rvv-related extensions.Extensions affected: +v, +zve*, +zvl*Reviewed By: craig.topperDifferential Revision: https://reviews.llvm.org/D117860 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/stepvector.ll Fri, 21 Jan 2022 08:39:23 +0000 eopXD <eop.chen@sifive.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/stepvector.ll#af0ecfcc [RISCV] Generate pseudo instruction liAdd an alias of `addi [x], zero, imm` to generate pseudoinstruction li, which makes assembly mush more readable.For existed tests, users can update them by running script`llvm/utils/update_llc_test_checks.py`.Reviewed By: asbDifferential Revision: https://reviews.llvm.org/D112692 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/stepvector.ll Mon, 22 Nov 2021 06:01:37 +0000 wangpc <pc.wang@linux.alibaba.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/stepvector.ll#facff468 [RISCV] Reorder the vector register allocation order.GPR uses argument registers as the first group of registers to allocate.This patch uses vector argument registers, v8 to v23, as the first groupto allocate.Differential Revision: https://reviews.llvm.org/D111304 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/stepvector.ll Thu, 07 Oct 2021 11:30:33 +0000 Hsiangkai Wang <kai.wang@sifive.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/stepvector.ll#f7076cfd [DAGCombiner][RISCV][AMDGPU] Call SimplifyDemandedBits at the end of visitMULHU to enable known bits contant folding.We don't have real demanded bits support for MULHU, but we canstill use the known bits based constant folding support at the endof SimplifyDemandedBits to simplify a MULHU. This helps with caseswhere we know the LHS and RHS have enough leading zeros so thatthe high multiply result is always 0.Reviewed By: RKSimonDifferential Revision: https://reviews.llvm.org/D106471 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/stepvector.ll Thu, 05 Aug 2021 15:31:24 +0000 Craig Topper <craig.topper@sifive.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/stepvector.ll#0ca46a17 [SelectionDAG] Fix the representation of ISD::STEP_VECTOR.The existing rule about the operand type is strange. Instead, just saythe operand is a TargetConstant with the right width. (Legalizationignores TargetConstants, so it doesn't matter if that width is legal.)Highlights:1. I had to substantially rewrite the AArch64 isel patterns to expect aTargetConstant. Nothing too exotic, but maybe a little hairy. Maybeworth considering a target-specific node with some dagcombines insteadof this complicated nest of isel patterns.2. Our behavior on RV32 for vectors of i64 has changed slightly. Inparticular, we correctly preserve the width of the arithmetic throughlegalization. This changes the DAG a bit. Maybe room forimprovement here.3. I explicitly defined the behavior around overflow. This is necessaryto make the DAGCombine transforms legal, and I don't think it causes anypractical issues.Differential Revision: https://reviews.llvm.org/D105673 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/stepvector.ll Thu, 08 Jul 2021 23:14:33 +0000 Eli Friedman <efriedma@quicinc.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/stepvector.ll#173332d1 [RISCV] Manually emit the best shift for VSCALE lowering to improve codegen.We assume VLENB is a multiple of 8 and previously relied on shiftpairs being optimized to an AND+SHL/SHR and computeKnownBitsremoving the AND. This doesn't happen if (vlenb >> 3) gets CSEdto have multiple uses. This patch manually emits the best shiftto workaround this. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/stepvector.ll Sat, 17 Jul 2021 07:24:48 +0000 Craig Topper <craig.topper@sifive.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/stepvector.ll#242ddd50 [RISCV][NFC] Add a single space after comma for VTypeIn most of cases, it has a single space after comma in assembly operands.Reviewed By: craig.topperDifferential Revision: https://reviews.llvm.org/D103790 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/stepvector.ll Tue, 08 Jun 2021 07:40:56 +0000 Jim Lin <jim@andestech.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/stepvector.ll#797e580d [RISCV][NFC] Simplify test run linesSeveral tests had -verify-machineinstrs twice, and several tests wereexplicitly specifying the default FileCheck prefix of CHECK. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/stepvector.ll Thu, 13 May 2021 11:35:03 +0000 Fraser Cormack <fraser@codeplay.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/stepvector.ll#d092dd56 [RISCV] Regenerate stepvector.ll. NFCIt looks like the RV32 and RV64 prefixes were removed from theRUN lines while another patch was in review that added checklines that used them. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/stepvector.ll Tue, 11 May 2021 19:24:56 +0000 Craig Topper <craig.topper@sifive.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/stepvector.ll#791766e6 [RISCV] Support STEP_VECTOR with a step greater than oneDAGCombiner was recently taught how to combine STEP_VECTOR nodes,meaning the step value is no longer guaranteed to be one by the time itreaches the backend for lowering.This patch supports such cases on RISC-V by lowering to other stepvalues to a multiply following the vid.v instruction. It includes asmall optimization for common cases where the multiply can be expressedas a shift left.Reviewed By: rogfer01Differential Revision: https://reviews.llvm.org/D100856 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/stepvector.ll Tue, 20 Apr 2021 14:23:30 +0000 Fraser Cormack <fraser@codeplay.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/stepvector.ll#978eb3f1 [DAGCombiner] Allow operand of step_vector to be negative.It is proper to relax non-negative limitation of step_vector.Also this patch adds more combines for step_vector:(sub X, step_vector(C)) -> (add X, step_vector(-C))Differential Revision: https://reviews.llvm.org/D100812 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/stepvector.ll Mon, 19 Apr 2021 09:16:08 +0000 Jun Ma <JunMa@linux.alibaba.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/stepvector.ll#457da7f2 [SelectionDAG] Relax constraints on STEP_VECTOR step operandThis patch relaxes the requirement that the STEP_VECTOR step constantmust be of a type at least as large as the vector element type. Thisdoes not permit its use on targets which have legal vector element typeslarger than the largest legal scalar type, such as i64 vectors on RV32.As such, the requirement has been loosened so that the step operand mustbe any scalar type so long as the constant immediate is non-negative andthe value fits inside the vector element type.This limits combining optimizations in certain circumstances but inpractice it's unlikely to be a hindrance.Reviewed By: paulwalker-armDifferential Revision: https://reviews.llvm.org/D100660 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/stepvector.ll Wed, 14 Apr 2021 08:03:27 +0000 Fraser Cormack <fraser@codeplay.com>