en Copyright 2015 Java http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll#9b0f227d [TableGen][RISCV] Add InstAliases with zero_reg to cover unmasked vnot.v, vncvt.x.x.w, vneg.v, etc.The mask being NoRegister prevented the existing aliases from matchingsince NoRegister isn't in the VMV0 register class.To workaround this I've added new aliases that look for zero_reg.I had to motify tablegen to generate matching code for zero_reg.And as a consequence, I had to change the EmitPriority for an ARMalias that used zero_reg that started printing.Reviewed By: frasercrmckDifferential Revision: https://reviews.llvm.org/D121496 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll Tue, 22 Mar 2022 16:53:39 +0000 Craig Topper <craig.topper@sifive.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll#bbd2ecf9 [RISCV] Add +experimental-zvfh extension to cover half types in vectors.Currently we allow half types in vectors if the scalar Zfh extensionis enabled. This behavior is not inline with the vector spec. For f32and f64 types, the Zve32f, Zve64f, Zve64d, and V explicitly controlthe availablity of floating point types in vectors.In order to make our compiler compliant, we either need to remove all supportfor half in vectors or we need an extension to control it.Draft spec here https://github.com/riscv/riscv-v-spec/pull/780Reviewed By: kito-chengDifferential Revision: https://reviews.llvm.org/D121345 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll Thu, 17 Mar 2022 16:44:43 +0000 Craig Topper <craig.topper@sifive.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll#c83905a3 [RISCV] Add inline expansion for vector fround.This avoids a crash for scalable vectors and or scalarization forfixed vectors.The algorithm is different enough that I don't think it makes senseto merge with ceil/floor/trunc. Algorithm is adapted from gcc's X86SSE2 output.Reviewed By: frasercrmckDifferential Revision: https://reviews.llvm.org/D117247 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll Fri, 04 Feb 2022 17:01:07 +0000 Craig Topper <craig.topper@sifive.com>