en Copyright 2015 Java http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll#c06d0b4d [RISCV] Add ADDI instr for computing FrameIndex addressRVV doesn't have immediate field for memory addressing. Currentlywe build MachineInstructions in PEI to computing stack offset forRVV load store instructions. These instructions were added too late tocan be optimized by CSE, LICM... passes.This patch makes FrameIndex SDNodes can't be matched in RVV Load Storeinstruction selection patterns. So that the FrameIndex SDNodes would beselected as `ADDI GPR, targetframeindex`.There are 2 advantages for such change:1. Stack objects address computing can be optimized by machine functionpasses.2. Since the ADDI instruction's destination register can be used as atemp register, we can save an emergency spill slot.Differential Revision: https://reviews.llvm.org/D128187 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll Sun, 19 Jun 2022 12:01:25 +0000 luxufan <luxufan@iscas.ac.cn> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll#3cf15af2 [RISCV] Remove experimental prefix from rvv-related extensions.Extensions affected: +v, +zve*, +zvl*Reviewed By: craig.topperDifferential Revision: https://reviews.llvm.org/D117860 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll Fri, 21 Jan 2022 08:39:23 +0000 eopXD <eop.chen@sifive.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll#af0ecfcc [RISCV] Generate pseudo instruction liAdd an alias of `addi [x], zero, imm` to generate pseudoinstruction li, which makes assembly mush more readable.For existed tests, users can update them by running script`llvm/utils/update_llc_test_checks.py`.Reviewed By: asbDifferential Revision: https://reviews.llvm.org/D112692 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll Mon, 22 Nov 2021 06:01:37 +0000 wangpc <pc.wang@linux.alibaba.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll#ada54585 [RISCV] Expand scalable vector bswap. Fix crash for bitreverse.Fix LegalizeVectorOps to not try shuffle or unrolling expansions forscalable vectors.Differential Revision: https://reviews.llvm.org/D112236 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll Fri, 29 Oct 2021 16:52:36 +0000 Craig Topper <craig.topper@sifive.com>