en Copyright 2015 Java http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/inline-asm.ll#75117fb3 [RISCV] Don't advertise i32->i64 zextload as free for RV64.The zextload hook is only used to determine whether to insert azero_extend or any_extend for narrow types leaving a basic block.Returning true from this hook tends to cause any load whose outputleaves the basic block to become an LWU instead of an LW.Since we tend to prefer sexts for i32 compares on RV64, this cancause extra sext.w instructions to be created in other basic blocks.If we use LW instead of LWU this gives the MIR pass from D116397a better chance of removing them.Another option might be to teach getPreferredExtendForValue inFunctionLoweringInfo.cpp about our preference for sign_extend ofi32 compares. That would cause SIGN_EXTEND to be chosen for anyvalue used by a compare instead of using the isZExtFree heuristic.That will require code to convert from the llvm::Type* to EVT/MVTas well as querying the type legalization actions to get thepromoted type in order to call TargetLowering::isSExtCheaperThanZExt.That seemed like many extra steps when no other target wants it.Though it would avoid us needing to lean on the MIR pass in some cases.Reviewed By: asbDifferential Revision: https://reviews.llvm.org/D116567 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/inline-asm.ll Thu, 06 Jan 2022 16:13:41 +0000 Craig Topper <craig.topper@sifive.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/inline-asm.ll#f430c1eb [Tests] Add elementtype attribute to indirect inline asm operands (NFC)This updates LLVM tests for D116531 by adding elementtype attributesto operands that correspond to indirect asm constraints. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/inline-asm.ll Thu, 06 Jan 2022 11:10:58 +0000 Nikita Popov <npopov@redhat.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/inline-asm.ll#4d5fd0ee [MC][RISCV] Set UseIntegratedAssembler to trueto align with most other targets. Also, -fintegrated-as is the defaultfor clang -target riscv*. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/inline-asm.ll Mon, 13 Jul 2020 04:04:31 +0000 Fangrui Song <maskray@google.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/inline-asm.ll#46e3edcc [RISCV] Fix test for inline asm z constraint modifierSummary: Use an `i` constraint in the test, to correctly trigger the code forhandling the `z` constraint modifier.Reviewers: asb, lenary, jrtc27Reviewed By: lenary, jrtc27Tags: #llvmDifferential Revision: https://reviews.llvm.org/D72134 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/inline-asm.ll Wed, 15 Jan 2020 13:47:23 +0000 Luís Marques <luismarques@lowrisc.org> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/inline-asm.ll#043c5eaf [RISCV] Handle globals and block addresses in asm operandsSummary: These seem to be the machine operand types currently needed by theRISC-V target.Reviewers: asb, lenaryReviewed By: lenaryTags: #llvmDifferential Revision: https://reviews.llvm.org/D72275 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/inline-asm.ll Mon, 13 Jan 2020 15:33:07 +0000 Luís Marques <luismarques@lowrisc.org> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/inline-asm.ll#c2b3d527 [RISCV] Fix a couple of tests' CHECKsllvm-svn: 370466 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/inline-asm.ll Fri, 30 Aug 2019 12:11:47 +0000 Luis Marques <luismarques@lowrisc.org> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/inline-asm.ll#7abf863f [RISCV] Lower inline asm constraint A for RISC-VThis allows arguments with the constraint A to be lowered to input nodesfor RISC-V, which implies a memory address stored in a register.This patch adds the minimal amount of code required to get operands withthe right constraints to compile.https://reviews.llvm.org/D54296llvm-svn: 369095 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/inline-asm.ll Fri, 16 Aug 2019 10:28:34 +0000 Lewis Revill <lewis.revill@embecosm.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/inline-asm.ll#e1e036a3 [RISCV] Support z and i operand modifiersDifferential Revision: https://reviews.llvm.org/D57792Patch by James Clarke.llvm-svn: 365291 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/inline-asm.ll Mon, 08 Jul 2019 05:00:26 +0000 Alex Bradbury <asb@lowrisc.org> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/inline-asm.ll#aa6f2af4 [RISCV] Fix inline-asm.ll test by adding nounwind attributeThis test failed since CFI directive support was added in r361320.llvm-svn: 363123 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/inline-asm.ll Wed, 12 Jun 2019 05:32:30 +0000 Alex Bradbury <asb@lowrisc.org> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/inline-asm.ll#28a5cadb [RISCV] Lower inline asm constraints I, J & K for RISC-VThis validates and lowers arguments to inline asm nodes which have theconstraints I, J & K, with the following semantics (equivalent to GCC):I: Any 12-bit signed immediate.J: Immediate integer zero only.K: Any 5-bit unsigned immediate.Differential Revision: https://reviews.llvm.org/D54093llvm-svn: 363054 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/inline-asm.ll Tue, 11 Jun 2019 12:42:13 +0000 Lewis Revill <lewis.revill@embecosm.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/inline-asm.ll#5dabe03b [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCVr360897 was incomplete, must have applied an old/wip patch. This is in preparation for emitting CFI directives.llvm-svn: 361493 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/inline-asm.ll Thu, 23 May 2019 12:43:13 +0000 Alex Bradbury <asb@lowrisc.org> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/inline-asm.ll#4efa0b67 [RISCV][NFC] Add RV64I CHECK lines to inline-asm.ll testllvm-svn: 354028 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/inline-asm.ll Thu, 14 Feb 2019 13:09:54 +0000 Alex Bradbury <asb@lowrisc.org> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/inline-asm.ll#0171a9f4 [RISCV] Peephole optimisation for load/store of global values or constant addresses(load (add base, off), 0) -> (load base, off)(store val, (add base, off)) -> (store val, base, off)This is similar to an equivalent peephole optimisation in PPCISelDAGToDAG.llvm-svn: 327831 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/inline-asm.ll Mon, 19 Mar 2018 11:54:28 +0000 Alex Bradbury <asb@lowrisc.org> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/inline-asm.ll#7d6aa1f7 [RISCV] Implement frame pointer eliminationllvm-svn: 322839 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/inline-asm.ll Thu, 18 Jan 2018 11:34:02 +0000 Alex Bradbury <asb@lowrisc.org> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/inline-asm.ll#9330e644 [RISCV] Add basic support for inline asm constraintsllvm-svn: 322217 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/inline-asm.ll Wed, 10 Jan 2018 20:05:09 +0000 Alex Bradbury <asb@lowrisc.org>