en Copyright 2015 Java http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/float-imm.ll#84bacb18 [RISCV] Use check-prefixes to reduce check linesReviewed By: frasercrmckDifferential Revision: https://reviews.llvm.org/D125083 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/float-imm.ll Fri, 03 Jun 2022 17:27:15 +0000 Shao-Ce SUN <sunshaoce@iscas.ac.cn> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/float-imm.ll#f69078b7 [RISCV] Update some tests to use floating point ABI where it makes sense.Trying to reduce the diffs from D118333 for cases where it makesmore sense to use an FP ABI.Reviewed By: asb, kito-chengDifferential Revision: https://reviews.llvm.org/D120447 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/float-imm.ll Thu, 24 Feb 2022 17:23:14 +0000 Craig Topper <craig.topper@sifive.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/float-imm.ll#969e7034 [RISCV] Support Constant Pools in Load/Store PeepholeSummary:RISC-V uses a post-select peephole pass to optimise`(load/store (ADDI $reg, %lo(addr)), 0)` into `(load/store $reg, %lo(addr))`.This peephole wasn't firing for accesses to constant pools, which is how wematerialise most floating point constants.This adds support for the constantpool case, which improves code generation forlots of small FP loading examples. I have not added any tests because thisstructure is well-covered by the `fp-imm.ll` testcases, as well as almostall other uses of floating point constants in the RISC-V backend tests.Reviewed By: luismarques, asbDifferential Revision: https://reviews.llvm.org/D79523 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/float-imm.ll Mon, 11 May 2020 17:52:42 +0000 Sam Elliott <selliott@lowrisc.org> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/float-imm.ll#3242e565 Revert "[RISCV] Support Constant Pools in Load/Store Peephole"This reverts commit fe69dfebcfa007e23bf528fff8b96ac63e593e34, due toa slight change in the API. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/float-imm.ll Mon, 11 May 2020 17:13:41 +0000 Sam Elliott <selliott@lowrisc.org> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/float-imm.ll#fe69dfeb [RISCV] Support Constant Pools in Load/Store PeepholeSummary:RISC-V uses a post-select peephole pass to optimise`(load/store (ADDI $reg, %lo(addr)), 0)` into `(load/store $reg, %lo(addr))`.This peephole wasn't firing for accesses to constant pools, which is how wematerialise most floating point constants.This adds support for the constantpool case, which improves code generation forlots of small FP loading examples. I have not added any tests because thisstructure is well-covered by the `fp-imm.ll` testcases, as well as almostall other uses of floating point constants in the RISC-V backend tests.Reviewed By: luismarques, asbDifferential Revision: https://reviews.llvm.org/D79523 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/float-imm.ll Mon, 11 May 2020 16:58:33 +0000 Sam Elliott <selliott@lowrisc.org> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/float-imm.ll#3d0fbafd [RISCV] Switch to the Machine SchedulerMost of the test changes are trivial instruction reorderings and differingregister allocations, without any obvious performance impact.Differential Revision: https://reviews.llvm.org/D66973llvm-svn: 372106 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/float-imm.ll Tue, 17 Sep 2019 11:15:35 +0000 Luis Marques <luismarques@lowrisc.org> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/float-imm.ll#2d550d19 Revert Patch from PhabricatorThis reverts r372092 (git commit e38695a0255c9e7b53639f349f8101bae1ce5c04)llvm-svn: 372104 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/float-imm.ll Tue, 17 Sep 2019 10:52:09 +0000 Luis Marques <luismarques@lowrisc.org> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/float-imm.ll#e38695a0 Patch from Phabricatorllvm-svn: 372092 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/float-imm.ll Tue, 17 Sep 2019 09:43:08 +0000 Luis Marques <luismarques@lowrisc.org> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/float-imm.ll#d834d830 [RISCV] Add RV64F codegen supportThis requires a little extra work due tothe fact i32 is not a legal type. Whencall lowering happens post-legalisation (e.g. when an intrinsic was insertedduring legalisation). A bitcast from f32 to i32 can't be introduced. This issimilar to the challenges with RV32D. To handle this, we introducetarget-specific DAG nodes that perform bitcast+anyext for f32->i64 andtrunc+bitcast for i64->f32.Differential Revision: https://reviews.llvm.org/D53235llvm-svn: 352807 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/float-imm.ll Thu, 31 Jan 2019 22:48:38 +0000 Alex Bradbury <asb@lowrisc.org> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/float-imm.ll#80c8eb76 [RISCV] Add codegen for RV32F floating point load/storeAs part of this, add support for load/store from the constant pool. This isused to materialise f32 constants.llvm-svn: 327979 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/float-imm.ll Tue, 20 Mar 2018 13:26:12 +0000 Alex Bradbury <asb@lowrisc.org>