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    <title>Changes in vec_revb.ll</title>
    <description></description>
    <language>en</language>
    <copyright>Copyright 2015</copyright>
    <generator>Java</generator><item>
        <title>2d989077 - [PowerPC] [NFC] Add AIX triple to some regression tests</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/vec_revb.ll#2d989077</link>
        <description>[PowerPC] [NFC] Add AIX triple to some regression testsAs part of the effort to improve AIX support, regression test coveragemisses quite a lot for AIX subtarget. This patch adds AIX triple tothose don&apos;t need extra change, and we can cover more cases in followingcommits.Reviewed By: steven.zhangDifferential Revision: https://reviews.llvm.org/D94159

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/vec_revb.ll</description>
        <pubDate>Mon, 18 Jan 2021 03:44:00 +0000</pubDate>
        <dc:creator>Qiu Chaofan &lt;qiucofan@cn.ibm.com&gt;</dc:creator>
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        <title>6d5e35e8 - [Power9] Remove the PPCISD::XXREVERSE as it has completely the same semantics of ISD::BSWAP</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/vec_revb.ll#6d5e35e8</link>
        <description>[Power9] Remove the PPCISD::XXREVERSE as it has completely the same semantics of ISD::BSWAPThe custom node PPCISD::XXREVERSE has completely the same semantics of generic node ISD::BSWAP.We need to clean up it as we have the combine rules for bswap in the base class, while nothing for xxreverse.Differential Revision: https://reviews.llvm.org/D70657

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/vec_revb.ll</description>
        <pubDate>Mon, 23 Dec 2019 07:41:31 +0000</pubDate>
        <dc:creator>QingShan Zhang &lt;qshanz@cn.ibm.com&gt;</dc:creator>
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        <title>bae5aac1 - [NFC][Test] Adding the test for bswap + logic op for PowerPC</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/vec_revb.ll#bae5aac1</link>
        <description>[NFC][Test] Adding the test for bswap + logic op for PowerPC

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/vec_revb.ll</description>
        <pubDate>Mon, 25 Nov 2019 08:21:12 +0000</pubDate>
        <dc:creator>QingShan Zhang &lt;qshanz@cn.ibm.com&gt;</dc:creator>
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        <title>25528d6d - [CodeGen] Unify MBB reference format in both MIR and debug output</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/vec_revb.ll#25528d6d</link>
        <description>[CodeGen] Unify MBB reference format in both MIR and debug outputAs part of the unification of the debug format and the MIR format, printMBB references as &apos;%bb.5&apos;.The MIR printer prints the IR name of a MBB only for block definitions.* find . \( -name &quot;*.mir&quot; -o -name &quot;*.cpp&quot; -o -name &quot;*.h&quot; -o -name &quot;*.ll&quot; \) -type f -print0 | xargs -0 sed -i &apos;&apos; -E &apos;s/BB#&quot; &lt;&lt; ([a-zA-Z0-9_]+)-&gt;getNumber\(\)/&quot; &lt;&lt; printMBBReference(*\1)/g&apos;* find . \( -name &quot;*.mir&quot; -o -name &quot;*.cpp&quot; -o -name &quot;*.h&quot; -o -name &quot;*.ll&quot; \) -type f -print0 | xargs -0 sed -i &apos;&apos; -E &apos;s/BB#&quot; &lt;&lt; ([a-zA-Z0-9_]+)\.getNumber\(\)/&quot; &lt;&lt; printMBBReference(\1)/g&apos;* find . \( -name &quot;*.txt&quot; -o -name &quot;*.s&quot; -o -name &quot;*.mir&quot; -o -name &quot;*.cpp&quot; -o -name &quot;*.h&quot; -o -name &quot;*.ll&quot; \) -type f -print0 | xargs -0 sed -i &apos;&apos; -E &apos;s/BB#([0-9]+)/%bb.\1/g&apos;* grep -nr &apos;BB#&apos; and fixDifferential Revision: https://reviews.llvm.org/D40422llvm-svn: 319665

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/vec_revb.ll</description>
        <pubDate>Mon, 04 Dec 2017 17:18:51 +0000</pubDate>
        <dc:creator>Francis Visoiu Mistrih &lt;francisvm@yahoo.com&gt;</dc:creator>
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        <title>1a8eec14 - [PowerPC] Match vec_revb builtins to P9 instructions.</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/vec_revb.ll#1a8eec14</link>
        <description>[PowerPC] Match vec_revb builtins to P9 instructions.Power9 has instructions that will reverse the bytes within an element for allsizes (half-word, word, double-word and quad-word). These can be used for thevec_revb builtins in altivec.h. However, we implement these to match vectorshuffle nodes as that will cover both the builtins and vector shuffles thatoccur in the SDAG through other means.Differential Revision: https://reviews.llvm.org/D33690llvm-svn: 305214

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/vec_revb.ll</description>
        <pubDate>Mon, 12 Jun 2017 18:24:36 +0000</pubDate>
        <dc:creator>Tony Jiang &lt;jtony@ca.ibm.com&gt;</dc:creator>
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