en Copyright 2015 Java http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/vec-trunc2.ll#335e8bf1 [PowerPC] emit VSX instructions instead of VMX instructions for vector loads and storesThis patch changes the PowerPC backend to generate VSX load/store instructionsfor all vector loads/stores on Power8 and earlier (LE) instead of VMXload/store instructions. The reason for this change is because VMX instructionsrequire the vector to be 16-byte aligned. So, a vector load/store will fail withVMX instructions if the vector is misaligned. Also, `gcc` generates VSXinstructions in this situation which allow for unaligned access but require aswap instruction after loading/before storing. This is not an issue for BEbecause we already emit VSX instructions since no swap is required. And this isnot an issue on Power9 and up since we have access to `lxv[x]`/`stxv[x]` whichallow for unaligned access and do not require swaps.This patch also delays the VSX load/store for LE combines until afterLegalizeOps to prioritize other load/store combines.Reviewed By: #powerpc, stefanpDifferential Revision: https://reviews.llvm.org/D127309 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/vec-trunc2.ll Wed, 08 Jun 2022 14:47:48 +0000 Quinn Pham <Quinn.Pham@ibm.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/vec-trunc2.ll#766ca2c5 [PowerPC] Add missed VSX shuffles instead of Altivec onesVSX introduced some permute instructions that are directreplacements for Altivec ones except they can target allthe VSX registers. We have added code generation for mostof these but somehow missed the low/hi word merges (XXMRG[LH]W).This caused some additional spills on some largecomputationally intensive code.This patch simply adds the missed patterns. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/vec-trunc2.ll Fri, 11 Mar 2022 17:19:20 +0000 Nemanja Ivanovic <nemanjai@ca.ibm.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/vec-trunc2.ll#8b6674e6 [NFC][Test] Update the test with update_llc_test_checks.py List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/vec-trunc2.ll Fri, 09 Oct 2020 02:26:03 +0000 QingShan Zhang <qshanz@cn.ibm.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/vec-trunc2.ll#b6d7ed46 [PowerPC] Extend custom lower of vector truncate to handle wider inputCurrent custom lowering of truncate vector handles a source of up to 128 bits, but that only uses one of the two shuffle vector operands. Extend it to use both operands to handle 256 bit sources.Differential Revision: https://reviews.llvm.org/D68035 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/vec-trunc2.ll Mon, 24 Aug 2020 19:30:04 +0000 Roland Froese <froese@ca.ibm.com>