en Copyright 2015 Java http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/vec-trunc.ll#335e8bf1 [PowerPC] emit VSX instructions instead of VMX instructions for vector loads and storesThis patch changes the PowerPC backend to generate VSX load/store instructionsfor all vector loads/stores on Power8 and earlier (LE) instead of VMXload/store instructions. The reason for this change is because VMX instructionsrequire the vector to be 16-byte aligned. So, a vector load/store will fail withVMX instructions if the vector is misaligned. Also, `gcc` generates VSXinstructions in this situation which allow for unaligned access but require aswap instruction after loading/before storing. This is not an issue for BEbecause we already emit VSX instructions since no swap is required. And this isnot an issue on Power9 and up since we have access to `lxv[x]`/`stxv[x]` whichallow for unaligned access and do not require swaps.This patch also delays the VSX load/store for LE combines until afterLegalizeOps to prioritize other load/store combines.Reviewed By: #powerpc, stefanpDifferential Revision: https://reviews.llvm.org/D127309 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/vec-trunc.ll Wed, 08 Jun 2022 14:47:48 +0000 Quinn Pham <Quinn.Pham@ibm.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/vec-trunc.ll#513976df [PowerPC] Ignore implicit register operands for MCInstSummary:When doing the conversion: MachineInst -> MCInst, we should ignore theimplicit operands, it will expose more opportunity for InstiAlias.Reviewed By: steven.zhangDifferential Revision: https://reviews.llvm.org/D77118 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/vec-trunc.ll Thu, 16 Apr 2020 16:22:43 +0000 Kang Zhang <shkzhang@cn.ibm.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/vec-trunc.ll#732fe224 [PowerPC] Avoid scalarization of vector truncateThe PowerPC code generator currently scalarizes vector truncates that would fit in a vector register, resulting in vector extracts, scalar operations, and vector merges. This patch custom lowers a vector truncate that would fit in a register to a vector shuffle instead.Differential Revision: https://reviews.llvm.org/D56507llvm-svn: 353724 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/vec-trunc.ll Mon, 11 Feb 2019 17:29:14 +0000 Roland Froese <froese@ca.ibm.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/vec-trunc.ll#42f58498 [PowerPC] Add vector truncate test to prep for D56507 NFCllvm-svn: 353344 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/vec-trunc.ll Wed, 06 Feb 2019 21:34:44 +0000 Roland Froese <froese@ca.ibm.com>