Changes in select-addrRegRegOnly.ll

1ed7d211 - [PowerPC] Support extended mnemonics mffprwz etc.

Thu, 29 Aug 2019 21:53:59 +0000

[PowerPC] Support extended mnemonics mffprwz etc.Summary:Reported in https://github.com/opencv/opencv/issues/15413.We have serveral extended mnemonics for Move To/From Vector-Scalar Register Instructionseg: mffprd,mtfprd etc.We only support one of them, this patch add the others.Reviewers: nemanjai, steven.zhang, hfinkel, #powerpcReviewed By: hfinkelSubscribers: wuzish, qcolombet, hiraditya, kbarton, MaskRay, shchenz, llvm-commitsTags: #llvmDifferential Revision: https://reviews.llvm.org/D66963llvm-svn: 370411 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/select-addrRegRegOnly.ll

cb4f0c5c - [PowerPC] Replace the Post RA List Scheduler with the Machine Scheduler

Wed, 04 Jul 2018 18:54:25 +0000

[PowerPC] Replace the Post RA List Scheduler with the Machine Scheduler We want to run the Machine Scheduler instead of the List Scheduler after RA. Checked with a performance run on a Power 9 machine with SPEC 2006 and while some benchmarks improved and others degraded the geomean was slightly improved with the Machine Scheduler. Differential Revision: https://reviews.llvm.org/D45265llvm-svn: 336295 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/select-addrRegRegOnly.ll

25528d6d - [CodeGen] Unify MBB reference format in both MIR and debug output

Mon, 04 Dec 2017 17:18:51 +0000

[CodeGen] Unify MBB reference format in both MIR and debug outputAs part of the unification of the debug format and the MIR format, printMBB references as '%bb.5'.The MIR printer prints the IR name of a MBB only for block definitions.* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g'* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g'* find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g'* grep -nr 'BB#' and fixDifferential Revision: https://reviews.llvm.org/D40422llvm-svn: 319665 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/select-addrRegRegOnly.ll

438bf4a6 - [PPC] Heuristic to choose between a X-Form VSX ld/st vs a X-Form FP ld/st.

Mon, 20 Nov 2017 14:38:30 +0000

[PPC] Heuristic to choose between a X-Form VSX ld/st vs a X-Form FP ld/st.The VSX versions have the advantage of a full 64-register target whereas the FPones have the advantage of lower latency and higher throughput. So what we’reafter is using the faster instructions in low register pressure situations andusing the larger register file in high register pressure situations.The heuristic chooses between the following 7 pairs of instructions.PPC::LXSSPX vs PPC::LFSXPPC::LXSDX vs PPC::LFDXPPC::STXSSPX vs PPC::STFSXPPC::STXSDX vs PPC::STFDXPPC::LXSIWAX vs PPC::LFIWAXPPC::LXSIWZX vs PPC::LFIWZXPPC::STXSIWX vs PPC::STFIWXDifferential Revision: https://reviews.llvm.org/D38486llvm-svn: 318651 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/select-addrRegRegOnly.ll

168d14b1 - [PowerPC] Reduce register pressure by not materializing a constant just for use as an index register for X-Form loads/stores.

Mon, 10 Jul 2017 16:44:45 +0000

[PowerPC] Reduce register pressure by not materializing a constant just for use as an index register for X-Form loads/stores.For this example:float test (int *arr) { return arr[2];}We currently generate the following code: li r4, 8 lxsiwax f0, r3, r4 xscvsxdsp f1, f0With this patch, we will now generate: addi r3, r3, 8 lxsiwax f0, 0, r3 xscvsxdsp f1, f0Originally reported in: https://bugs.llvm.org/show_bug.cgi?id=27204Differential Revision: https://reviews.llvm.org/D35027llvm-svn: 307553 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/select-addrRegRegOnly.ll