en Copyright 2015 Java http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/p10-vector-shift.ll#cb0c034e [PowerPC] Fix issue where vsrq is given incorrect shift vectorThe new Power10 instruction vsrq was being given the wrong shift vector.The original code assumed that the shift would be found in bits 121 to 127.This is not correct. The shift is found in bits 57 to 63.This can be fixed by swaping the first and second double words.Reviewed By: nemanjai, #powerpcDifferential Revision: https://reviews.llvm.org/D94113 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/p10-vector-shift.ll Tue, 05 Jan 2021 20:42:53 +0000 Stefan Pintilie <stefanp@ca.ibm.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/p10-vector-shift.ll#3136cbe2 [PowerPC] Implement Vector Shift BuiltinsThis patch implements the builtins for the vector shifts (shl, srl, sra), andadds the appropriate test cases for these builtins. The builtins utilize thevector shift instructions introduced within ISA 3.1.Differential Revision: https://reviews.llvm.org/D83338 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/p10-vector-shift.ll Wed, 12 Aug 2020 23:26:43 +0000 Albion Fung <albionapc@gmail.com>