Changes in fold-zero.ll

86e3abc9 - [PowerPC] Add some InstAlias definitions

Sun, 24 May 2020 14:05:28 +0000

[PowerPC] Add some InstAlias definitionsSummary:This patch add the InstAlias definitions for below instructions.ADDI ADDIS ADDI8 ADDIS8RLWINM8ISEL ISEL8OR OR_rec ORI ORI8 XORI8CNTLZW8 CNTLZW8_recTEND TSRRFEBBNOR NOR_recMTCRFSUBF SUBF_rec SUBFC SUBFC_recRLDICL_32_64TWReviewed By: steven.zhangDifferential Revision: https://reviews.llvm.org/D77559 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/fold-zero.ll

8e8c444d - [PowerPC] Expand ISEL instruction into if-then-else sequence.

Mon, 16 Jan 2017 20:12:26 +0000

[PowerPC] Expand ISEL instruction into if-then-else sequence.Generally, the ISEL is expanded into if-then-else sequence, in somecases (like when the destination register is the same with the trueor false value register), it may just be expanded into just the ifor else sequence.llvm-svn: 292154 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/fold-zero.ll

8da139a9 - Revert "[PowerPC] Expand ISEL instruction into if-then-else sequence."

Mon, 16 Jan 2017 15:01:07 +0000

Revert "[PowerPC] Expand ISEL instruction into if-then-else sequence."This reverts commit 1d0e0374438ca6e153844c683826ba9b82486bb1.llvm-svn: 292131 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/fold-zero.ll

7630b8c5 - [PowerPC] Expand ISEL instruction into if-then-else sequence.

Mon, 16 Jan 2017 14:43:12 +0000

[PowerPC] Expand ISEL instruction into if-then-else sequence.Generally, the ISEL is expanded into if-then-else sequence, in somecases (like when the destination register is the same with the trueor false value register), it may just be expanded into just the ifor else sequence.llvm-svn: 292128 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/fold-zero.ll

a538b0f0 - Adding -verify-machineinstrs option to PowerPC tests

Wed, 03 Aug 2016 18:17:35 +0000

Adding -verify-machineinstrs option to PowerPC testsCurrently we have a number of tests that fail with -verify-machineinstrs.To detect this cases earlier we add the option to the testcases with theexception of tests that will currently fail with this option. PR 27456 keepstrack of this failures.No code review, as discussed with Hal Finkel.llvm-svn: 277624 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/fold-zero.ll

940ab934 - Add CR-bit tracking to the PowerPC backend for i1 values

Fri, 28 Feb 2014 00:27:01 +0000

Add CR-bit tracking to the PowerPC backend for i1 valuesThis change enables tracking i1 values in the PowerPC backend using thecondition register bits. These bits can be treated on PowerPC as separateregisters; individual bit operations (and, or, xor, etc.) are supported.Tracking booleans in CR bits has several advantages: - Reduction in register pressure (because we no longer need GPRs to store boolean values). - Logical operations on booleans can be handled more efficiently; we used to have to move all results from comparisons into GPRs, perform promoted logical operations in GPRs, and then move the result back into condition register bits to be used by conditional branches. This can be very inefficient, because the throughput of these CR <-> GPR moves have high latency and low throughput (especially when other associated instructions are accounted for). - On the POWER7 and similar cores, we can increase total throughput by using the CR bits. CR bit operations have a dedicated functional unit.Most of this is more-or-less mechanical: Adjustments were needed in thecalling-convention code, support was added for spilling/restoring individualcondition-register bits, and conditional branch instruction definitions takingspecific CR bits were added (plus patterns and code for generating bit-leveloperations).This is enabled by default when running at -O2 and higher. For -O0 and -O1,where the ability to debug is more important, this feature is disabled bydefault. Individual CR bits do not have assigned DWARF register numbers,and storing values in CR bits makes them invisible to the debugger.It is critical, however, that we don't move i1 values that have been promotedto larger values (such as those passed as function arguments) into bitregisters only to quickly turn around and move the values back into GPRs (suchas happens when values are returned by functions). A pair of target-specificDAG combines are added to remove the trunc/extends in: trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)and: zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)In short, we only want to use CR bits where some of the i1 values come fromcomparisons or are used by conditional branches or selects. To put it anotherway, if we can do the entire i1 computation in GPRs, then we probably should(on the POWER7, the GPR-operation throughput is higher, and for all cores, theCR <-> GPR moves are expensive).POWER7 test-suite performance results (from 10 runs in each configuration):SingleSource/Benchmarks/Misc/mandel-2: 35% speedupMultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedupMultiSource/Benchmarks/MiBench/automotive-susan: 23% speedupSingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedupSingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedupSingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedupSingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdownMultiSource/Applications/lemon/lemon: 8% slowdownllvm-svn: 202451 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/fold-zero.ll

d61d4f80 - Implement PPCInstrInfo::FoldImmediate

Sat, 06 Apr 2013 19:30:30 +0000

Implement PPCInstrInfo::FoldImmediateThere are certain PPC instructions into which we can fold a zero immediateoperand. We can detect such cases by looking at the register class requiredby the using operand (so long as it is not otherwise constrained).llvm-svn: 178961 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/fold-zero.ll