Changes in fast-isel-cmp-imm.ll

308a609c - [PowerPC] Enhance the fast selection of cmp instruction and clean up related asserts

Fri, 25 Jan 2019 07:24:59 +0000

[PowerPC] Enhance the fast selection of cmp instruction and clean up related assertsFast selection of llvm icmp and fcmp instructions is not handled well about VSX instruction support.We'd use VSX float comparison instruction instead of non-vsx float comparison instruction if the operand register class is VSSRC or VSFRC because i32 and i64 are mapped to VSSRC and VSFRC correspondingly if VSX feature is opened.If the target does not have corresponding VSX instruction comparison for some type, just copy VSX-related register to common float register class and use non-vsx comparison instruction.Differential Revision: https://reviews.llvm.org/D57078llvm-svn: 352174 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll

d52990c7 - Introduce codegen for the Signal Processing Engine

Wed, 18 Jul 2018 04:25:10 +0000

Introduce codegen for the Signal Processing EngineSummary:The Signal Processing Engine (SPE) is found on NXP/Freescale e500v1,e500v2, and several e200 cores. This adds support targeting the e500v2,as this is more common than the e500v1, and is in SoCs still on themarket.This patch is very intrusive because the SPE is binary incompatible withthe traditional FPU. After discussing with others, the cleanestsolution was to make both SPE and FPU features on top of a base PowerPCsubset, so all FPU instructions are now wrapped with HasFPU predicates.Supported by this are:* Code generation following the SPE ABI at the LLVM IR level (callingconventions)* Single- and Double-precision math at the level supported by the APU.Still to do:* Vector operations* SPE intrinsicsAs this changes the Callee-saved register list order, one test, whichtests the precise generated code, was updated to account for the newregister order.Reviewed by: nemanjaiDifferential Revision: https://reviews.llvm.org/D44830llvm-svn: 337347 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll

1fb23395 - Clean up function attributes on PPC fast-isel tests.

Fri, 24 Jul 2015 01:07:50 +0000

Clean up function attributes on PPC fast-isel tests.llvm-svn: 243079 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll

7c5cb066 - [PowerPC] Enable printing instructions using aliases

Thu, 23 Apr 2015 18:30:38 +0000

[PowerPC] Enable printing instructions using aliasesTableGen had been nicely generating code to print a number of instructions usingshorter aliases (and PowerPC has plenty of short mnemonics), but we were notcalling it. For some of the aliases we support in the parser, TableGen can'tinfer the "inverse" alias relationship, so there is still more to do.Thus, after some hours of updating test cases...llvm-svn: 235616 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll

945a660c - Change the fast-isel-abort option from bool to int to enable "levels"

Fri, 27 Feb 2015 18:32:11 +0000

Change the fast-isel-abort option from bool to int to enable "levels"Summary:Currently fast-isel-abort will only abort for regular instructions,and just warn for function calls, terminators, function arguments.There is already fast-isel-abort-args but nothing for calls andterminators.This change turns the fast-isel-abort options into an integer option,so that multiple levels of strictness can be defined.This will help no being surprised when the "abort" option indeed doesnot abort, and enables the possibility to write test that verifiesthat no intrinsics are forgotten by fast-isel.Reviewers: resistor, echristoSubscribers: jfb, llvm-commitsDifferential Revision: http://reviews.llvm.org/D7941From: Mehdi Amini llvm-svn: 230775 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll

87982a1e - [PowerPC] Temporarily disable VSX for PowerPC fast-isel tests

Sun, 19 Oct 2014 20:48:47 +0000

[PowerPC] Temporarily disable VSX for PowerPC fast-isel testsPatch by Bill Seurer; some comment formatting changes by me.There are a few PowerPC test cases for FastISel support that currentlyfail with VSX support enabled. The temporary workaround underdiscussion in http://reviews.llvm.org/D5362 helps, but the tests stillfail because they specify -fast-isel-abort, and the VSX workaroundpunts back to SelectionDAG. We have plans to fix FastISel permanentlyfor VSX, but until that's in place these tests are preventing us fromenabling VSX by default. Therefore we are adding -mattr=-vsx to thesetests until the full support is ready.llvm-svn: 220172 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll

057b04f6 - [PowerPC] Handle selection of compare instructions in fast-isel.

Fri, 30 Aug 2013 03:16:48 +0000

[PowerPC] Handle selection of compare instructions in fast-isel.Mostly trivial patch adding support for compares. The meat of thework was added with the branch support.llvm-svn: 189639 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll