Changes in build-vector-tests.ll

335e8bf1 - [PowerPC] emit VSX instructions instead of VMX instructions for vector loads and stores

Wed, 08 Jun 2022 14:47:48 +0000

[PowerPC] emit VSX instructions instead of VMX instructions for vector loads and storesThis patch changes the PowerPC backend to generate VSX load/store instructionsfor all vector loads/stores on Power8 and earlier (LE) instead of VMXload/store instructions. The reason for this change is because VMX instructionsrequire the vector to be 16-byte aligned. So, a vector load/store will fail withVMX instructions if the vector is misaligned. Also, `gcc` generates VSXinstructions in this situation which allow for unaligned access but require aswap instruction after loading/before storing. This is not an issue for BEbecause we already emit VSX instructions since no swap is required. And this isnot an issue on Power9 and up since we have access to `lxv[x]`/`stxv[x]` whichallow for unaligned access and do not require swaps.This patch also delays the VSX load/store for LE combines until afterLegalizeOps to prioritize other load/store combines.Reviewed By: #powerpc, stefanpDifferential Revision: https://reviews.llvm.org/D127309 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/build-vector-tests.ll

666ee849 - [PowerPC] Fix shift amount of xxsldwi when performing vector int_to_double

Fri, 06 Aug 2021 06:00:57 +0000

[PowerPC] Fix shift amount of xxsldwi when performing vector int_to_doublePOC```// main.c#include #include extern vector double foo(vector int s);int main() { vector int s = {0, 1, 0, 4}; vector double vd; vd = foo(s); printf("%lf %lf\n", vd[0], vd[1]); return 0;}// poc.cvector double foo(vector int s) { int x1 = s[1]; int x3 = s[3]; double d1 = x1; double d3 = x3; vector double x = { d1, d3 }; return x;}```Compiled with `poc.c main.c -mcpu=pwr8 -O3` on BE machine.Current clang gives```4.000000 1.000000```while xlc gives```1.000000 4.000000```Xlc's output should be correct.Reviewed By: shchenz, #powerpcDifferential Revision: https://reviews.llvm.org/D107428 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/build-vector-tests.ll

ba627a32 - [PowerPC] Update Refactored Load/Store Implementation, XForm VSX Patterns, and Tests

Wed, 14 Jul 2021 01:33:23 +0000

[PowerPC] Update Refactored Load/Store Implementation, XForm VSX Patterns, and TestsThis patch includes the following updates to the load/store refactoring effort introduced in D93370: - Update various VSX patterns that use to "force" an XForm, to instead just XForm. This allows the ability for the patterns to compute the most optimal addressing mode (and to produce a DForm instruction when possible)- Update pattern and test case for the LXVD2X/STXVD2X intrinsics- Update LIT test cases that use to use the XForm instruction to use the DForm instructionDifferential Revision: https://reviews.llvm.org/D95115 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/build-vector-tests.ll

092619cf - [PowerPC] Improve codegen for vector fp to int widening conversions

Thu, 22 Apr 2021 03:16:35 +0000

[PowerPC] Improve codegen for vector fp to int widening conversionsWe currently do not utilize instructions that convert singleprecision vectors to doubleword integer vectors. These conversionscome up in code occasionally and this improvement allows us toopen code some functions that need to be added to altivec.h. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/build-vector-tests.ll

03e7feff - [PowerPC] Canonicalize shuffles on big endian targets as well

Tue, 20 Apr 2021 11:25:18 +0000

[PowerPC] Canonicalize shuffles on big endian targets as wellExtend shuffle canonicalization and conversion of shuffles fed by vectorizedscalars to big endian subtargets. For big endian subtargets, loads and directmoves of scalars into vector registers put the data in the correct element forSCALAR_TO_VECTOR if the data type is 8 bytes wide. However, if the data type isnarrower, the value still ends up in the wrong place - althouth a differentwrong place than on little endian targets.This patch extends the combine that keeps values where they are if they feed ashuffle to big endian targets.Differential revision: https://reviews.llvm.org/D100478 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/build-vector-tests.ll

1fed1316 - [PowerPC] Canonicalize shuffles to match more single-instruction masks on LE

Fri, 19 Jun 2020 02:53:50 +0000

[PowerPC] Canonicalize shuffles to match more single-instruction masks on LEWe currently miss a number of opportunities to emit single-instructionVMRG[LH][BHW] instructions for shuffles on little endian subtargets. Althoughthis in itself is not a huge performance opportunity since loading the permutevector for a VPERM can always be pulled out of loops, producing such mergeinstructions is useful to downstream optimizations.Since VPERM is essentially opaque to all subsequent optimizations, we want toavoid it as much as possible. Other permute instructions have semantics that canbe reasoned about much more easily in later optimizations.This patch does the following:- Canonicalize shuffles so that the first element comes from the first vector (since that's what most of the mask matching functions want)- Switch the elements that come from splat vectors so that they match the corresponding elements from the other vector (to allow for merges)- Adds debugging messages for when a shuffle is matched to a VPERM so that anyone interested in improving this further can get the info for their codeDifferential revision: https://reviews.llvm.org/D77448 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/build-vector-tests.ll

513976df - [PowerPC] Ignore implicit register operands for MCInst

Thu, 16 Apr 2020 16:22:43 +0000

[PowerPC] Ignore implicit register operands for MCInstSummary:When doing the conversion: MachineInst -> MCInst, we should ignore theimplicit operands, it will expose more opportunity for InstiAlias.Reviewed By: steven.zhangDifferential Revision: https://reviews.llvm.org/D77118 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/build-vector-tests.ll

ecd84354 - [NFC][PowerPC] Fix register class for patterns using XXPERMDIs

Tue, 07 Apr 2020 19:04:19 +0000

[NFC][PowerPC] Fix register class for patterns using XXPERMDIsThere are a few patterns where we use a superclass for inputs to thisinstruction rather than the correct class. This can sometimes lead tounncessary copies. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/build-vector-tests.ll

bfa9ce1c - [PowerPC] Improve handling of some BUILD_VECTOR nodes

Mon, 23 Mar 2020 22:34:05 +0000

[PowerPC] Improve handling of some BUILD_VECTOR nodesAn analysis of real world code turned up a number of patterns with BUILD_VECTORof nodes resulting from operations on extracted vector elements for which weproduce poor code. This addresses those cases. No attempt is made forcompleteness as that would entail a large amount of work for something thatthere is no evidence of in real code.Differential revision: https://reviews.llvm.org/D72660 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/build-vector-tests.ll

228dd96c - [PowerPC] Remove allow-deprecated-dag-overlap and fix broken tests

Tue, 12 Nov 2019 15:00:09 +0000

[PowerPC] Remove allow-deprecated-dag-overlap and fix broken testsSummary:This is found during review of https://reviews.llvm.org/D67088.CHECK-DAG is non-overlapping after https://reviews.llvm.org/D47106.-allow-deprecated-dag-overlap was introduced to temporary accept oldbehavior.But it actually hide some broken tests, eg: `test/CodeGen/PowerPC/swaps-le-1.ll`The codegen has changed, but the CHECK-DAG still PASS due to allowing `overlap`.This patch remove the deprecated options, and fix the broken tests.Reviewers: #powerpc, hfinkel, nemanjai, steven.zhang, shchenzReviewed By: shchenzSubscribers: shchenz, llvm-commitsTags: #llvmDifferential Revision: https://reviews.llvm.org/D69733 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/build-vector-tests.ll

cf57be9d - [PowerPC][NFC] Remove deprecated Function Attrs comments

Tue, 22 Oct 2019 21:28:15 +0000

[PowerPC][NFC] Remove deprecated Function Attrs comments List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/build-vector-tests.ll

1461fb6e - [PowerPC] Exploit single instruction load-and-splat for word and doubleword

Tue, 17 Sep 2019 16:45:20 +0000

[PowerPC] Exploit single instruction load-and-splat for word and doublewordWe currently produce a load, followed by (possibly a move for integers and) asplat as separate instructions. VSX has always had a splatting load fordoublewords, but as of Power9, we have it for words as well. This patch justexploits these instructions.Differential revision: https://reviews.llvm.org/D63624llvm-svn: 372139 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/build-vector-tests.ll

37cd0dd2 - [PowerPC][NFC] Remove duplicate tests in build-vector-test.ll

Wed, 14 Aug 2019 19:06:59 +0000

[PowerPC][NFC] Remove duplicate tests in build-vector-test.llAllOnes has been split into build-vector-allones.ll.llvm-svn: 368900 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/build-vector-tests.ll

66c32090 - recommit:[PowerPC] Eliminate loads/swap feeding swap/store for vector type by using big-endian load/store

Thu, 01 Aug 2019 05:26:02 +0000

recommit:[PowerPC] Eliminate loads/swap feeding swap/store for vector type by using big-endian load/storeIn PowerPC, there is instruction to load vector in big endian element order when it's in little endian target. So we can combine vector load + reverse into big endian load to eliminate the swap instruction.Also combine vector reverse + store into big endian store.Differential Revision: https://reviews.llvm.org/D65063llvm-svn: 367516 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/build-vector-tests.ll

54d446f7 - revert r367382 because buildbot failure

Wed, 31 Jul 2019 07:03:42 +0000

revert r367382 because buildbot failurellvm-svn: 367388 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/build-vector-tests.ll

e85f6bf6 - [PowerPC] Eliminate loads/swap feeding swap/store for vector type by using big-endian load/store

Wed, 31 Jul 2019 02:56:00 +0000

[PowerPC] Eliminate loads/swap feeding swap/store for vector type by using big-endian load/storeIn PowerPC, there is instruction to load vector in big endian element order when it's in little endian target. So we can combine vector load + reverse into big endian load to eliminate the swap instruction.Also combine vector reverse + store into big endian store.llvm-svn: 367382 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/build-vector-tests.ll

7aafdef6 - [MachineScheduler] checkResourceLimit boundary condition update

Fri, 07 Jun 2019 14:54:47 +0000

[MachineScheduler] checkResourceLimit boundary condition updateWhen we call checkResourceLimit in bumpCycle or bumpNode, and weknow the resource count has just reached the limit (the equations are equal). We should return true to mark that we are resourcelimited for next schedule, or else we might continue to schedulein favor of latency for 1 more schedule and create a schedule that actually overbook the resource.When we call checkResourceLimit to estimate the resource limite beforescheduling, we don't need to return true even if the equations areequal, as it shouldn't limit the schedule for it .Differential Revision: https://reviews.llvm.org/D62345llvm-svn: 362805 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/build-vector-tests.ll

3144d7a2 - [PowerPC] P9 Scheduling Model: dispatching rule fixes

Tue, 04 Jun 2019 15:22:23 +0000

[PowerPC] P9 Scheduling Model: dispatching rule fixesThis is to address some of the problems in existing P9 resource modeling,especially about the dispatching rules.Instead of using a hypothetical DISPATCHER , we try to use the number ofactual dispatch slots, and define SchedWriteRes to model dispatch rules,then update instruction classes according to dispatch rules.All the dispatch rules and instruction classes update are made accordingto POWER9 User Manual.Differential Revision: https://reviews.llvm.org/D61873llvm-svn: 362509 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/build-vector-tests.ll

9970665f - [PowerPC] [ISEL] select x-form instruction for unaligned offset

Wed, 22 May 2019 02:57:31 +0000

[PowerPC] [ISEL] select x-form instruction for unaligned offsetDifferential Revision: https://reviews.llvm.org/D62173llvm-svn: 361346 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/build-vector-tests.ll

cc63db4f - [PowerPC][NFC] Update build-vector-tests.ll using utils/update_llc_test_checks.py

Tue, 07 May 2019 17:29:44 +0000

[PowerPC][NFC] Update build-vector-tests.ll using utils/update_llc_test_checks.pybuild-vector-tests.ll is a huge testcase, it is hard to maintain: eg:any fundamental changes might need to update hundreds of lines. We shouldleverage the script to maintain it.This patch simply run utils/update_llc_test_checks.py on it. Thereshould be no missing test points.llvm-svn: 360175 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/build-vector-tests.ll