Changes in atomic-2.ll

a02a3fee - [PowerPC] Fix assert from machine verify pass that atomic pseudo expanding causes mismatched register class

Fri, 28 Dec 2018 02:12:55 +0000

[PowerPC] Fix assert from machine verify pass that atomic pseudo expanding causes mismatched register classFor atomic value operand which less than 4 bytes need to be masked. And the related operation to calculate the newvalue can be done in 32 bit gprc. So just use gprc for mask and value calculation.Differential Revision: https://reviews.llvm.org/D56077llvm-svn: 350113 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/atomic-2.ll

e2d2ce9f - PowerPC: Do not use llc -march in tests.

Tue, 01 Aug 2017 22:20:41 +0000

PowerPC: Do not use llc -march in tests.`llc -march` is problematic because it only switches the targetarchitecture, but leaves the operating system unchanged. Thisoccasionally leads to indeterministic tests because the OS fromLLVM_DEFAULT_TARGET_TRIPLE is used.However we can simply always use `llc -mtriple` instead. This changesall the tests to do this to avoid people using -march when they copy andpaste parts of tests.This patch:- Removes -march if the .ll file already has a matching `target triple` directive or -mtriple argument.- In all other cases changes -march=ppc32/-march=ppc64 to -mtriple=ppc32--/-mtriple=ppc64--See also the discussion in https://reviews.llvm.org/D35287llvm-svn: 309754 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/atomic-2.ll

7a08bb14 - [PowerPC] fix potential verification errors on CFENCE8

Thu, 15 Jun 2017 16:51:28 +0000

[PowerPC] fix potential verification errors on CFENCE8This patch fixes a potential verification error (64-bit register operands for cmpw) with -verify-machineinstrs.Differential Revision: https://reviews.llvm.org/D34208llvm-svn: 305479 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/atomic-2.ll

0fbbef43 - [PPC] Add -ppc-asm-full-reg-names to atomic-2.ll. NFC.

Tue, 16 May 2017 20:58:55 +0000

[PPC] Add -ppc-asm-full-reg-names to atomic-2.ll. NFC.Differential Revisions: https://reviews.llvm.org/D32763llvm-svn: 303209 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/atomic-2.ll

3bef27cc - [PPC] Lower load acquire/seq_cst trailing fence to cmp + bne + isync.

Tue, 16 May 2017 20:18:06 +0000

[PPC] Lower load acquire/seq_cst trailing fence to cmp + bne + isync.Summary:This fixes pr32392.The lowering pipeline is:llvm.ppc.cfence in IR -> PPC::CFENCE8 in isel -> Actual instructions inexpandPostRAPseudo.The reason why expandPostRAPseudo is chosen is because previous passesare likely eliminating instructions like cmpw 3, 3 (early CSE) and bne-7, .+4 (some branch pass(s)).Differential Revision: https://reviews.llvm.org/D32763llvm-svn: 303205 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/atomic-2.ll

a819cda0 - [PowerPC] Add triple to test/CodeGen/PowerPC/atomic-2.ll for ppc64le

Tue, 30 Aug 2016 00:22:22 +0000

[PowerPC] Add triple to test/CodeGen/PowerPC/atomic-2.ll for ppc64leOtherwise, running the test on Darwin systems will not work.llvm-svn: 280034 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/atomic-2.ll

3d70a9db - [PowerPC] Fix i8/i16 atomics for little-Endian targets without partword atomics

Mon, 29 Aug 2016 22:25:36 +0000

[PowerPC] Fix i8/i16 atomics for little-Endian targets without partword atomicsFor little-Endian PowerPC, we generally target only P8 and later by default.However, generic (older) 64-bit configurations are still an option, and in thatcase, partword atomics are not available (e.g. stbcx.). To lower i8/i16 atomicswithout true i8/i16 atomic operations, we emulate using i32 atomics incombination with a bunch of shifting and masking, etc. The amount by which toshift in little-Endian mode is different from the amount in big-Endian mode (itis inverted -- meaning we can leave off the xor when computing the amount).Fixes PR22923.llvm-svn: 280022 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/atomic-2.ll

7c5cb066 - [PowerPC] Enable printing instructions using aliases

Thu, 23 Apr 2015 18:30:38 +0000

[PowerPC] Enable printing instructions using aliasesTableGen had been nicely generating code to print a number of instructions usingshorter aliases (and PowerPC has plenty of short mnemonics), but we were notcalling it. For some of the aliases we support in the parser, TableGen can'tinfer the "inverse" alias relationship, so there is still more to do.Thus, after some hours of updating test cases...llvm-svn: 235616 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/atomic-2.ll

58f5f9c3 - [PowerPC] Disable part-word atomics on the P7

Sat, 11 Apr 2015 13:40:36 +0000

[PowerPC] Disable part-word atomics on the P7As it turns out, even though these are part of ISA 2.06, the P7 does notsupport them (or, at least, not any P7s we're tested so far).llvm-svn: 234686 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/atomic-2.ll

0adf26b9 - Add support for part-word atomics for PPC

Tue, 10 Mar 2015 20:51:07 +0000

Add support for part-word atomics for PPChttp://reviews.llvm.org/D8090#inline-67337llvm-svn: 231843 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/atomic-2.ll

a79ac14f - [opaque pointer type] Add textual IR support for explicit type parameter to load instruction

Fri, 27 Feb 2015 21:17:42 +0000

[opaque pointer type] Add textual IR support for explicit type parameter to load instructionEssentially the same as the GEP change in r230786.A similar migration script can be used to update test cases, though a few moretest case improvements/changes were required this time around: (r229269-r229278)import fileinputimport sysimport repat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace$\d+$ *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))Reviewers: rafael, dexonsmith, grosserDifferential Revision: http://reviews.llvm.org/D7649llvm-svn: 230794 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/atomic-2.ll

e1ca44bd - [Power] Improve the expansion of atomic loads/stores

Thu, 02 Oct 2014 22:27:07 +0000

[Power] Improve the expansion of atomic loads/storesSummary:Atomic loads and store of up to the native size (32 bits, or 64 for PPC64)can be lowered to a simple load or store instruction (as the synchronizationis already handled by AtomicExpand, and the atomicity is guaranteed thanks tothe alignment requirements of atomic accesses). This is exactly what this patchdoes. Previously, these were implemented by complexload-linked/store-conditional loops.. an obvious performance problem.For example, this patch turns```define void @store_i8_unordered(i8* %mem) { store atomic i8 42, i8* %mem unordered, align 1 ret void}```from```_store_i8_unordered: ; @store_i8_unordered; BB#0: rlwinm r2, r3, 3, 27, 28 li r4, 42 xori r5, r2, 24 rlwinm r2, r3, 0, 0, 29 li r3, 255 slw r4, r4, r5 slw r3, r3, r5 and r4, r4, r3LBB4_1: ; =>This Inner Loop Header: Depth=1 lwarx r5, 0, r2 andc r5, r5, r3 or r5, r4, r5 stwcx. r5, 0, r2 bne cr0, LBB4_1; BB#2: blr```into```_store_i8_unordered: ; @store_i8_unordered; BB#0: li r2, 42 stb r2, 0(r3) blr```which looks like a pretty clear win to me.Test Plan:fixed the tests + new test for indexed accesses + make check-allReviewers: jfb, wschmidt, hfinkelSubscribers: llvm-commitsDifferential Revision: http://reviews.llvm.org/D5587llvm-svn: 218922 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/atomic-2.ll

420a2168 - IR: add "cmpxchg weak" variant to support permitted failure.

Fri, 13 Jun 2014 14:24:07 +0000

IR: add "cmpxchg weak" variant to support permitted failure.This commit adds a weak variant of the cmpxchg operation, as describedin C++11. A cmpxchg instruction with this modifier is permitted tofail to store, even if the comparison indicated it should.As a result, cmpxchg instructions must return a flag indicatingsuccess in addition to their original iN value loaded. Thus, foruniformity *all* cmpxchg instructions now return "{ iN, i1 }". Thesecond flag is 1 when the store succeeded.At the DAG level, a new ATOMIC_CMP_SWAP_WITH_SUCCESS node has beenadded as the natural representation for the new cmpxchg instructions.It is a strong cmpxchg.By default this gets Expanded to the existing ATOMIC_CMP_SWAP duringLegalization, so existing backends should see no change in behaviour.If they wish to deal with the enhanced node instead, they can callsetOperationAction on it. Beware: as a node with 2 results, it cannotbe selected from TableGen.Currently, no use is made of the extra information provided in thispatch. Test updates are almost entirely adapting the input IR to thenew scheme.Summary for out of tree users:------------------------------+ Legacy Bitcode files are upgraded during read.+ Legacy assembly IR files will be invalid.+ Front-ends must adapt to different type for "cmpxchg".+ Backends should be unaffected by default.llvm-svn: 210903 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/atomic-2.ll

e94a518a - IR: add a second ordering operand to cmpxhg for failure

Tue, 11 Mar 2014 10:48:52 +0000

IR: add a second ordering operand to cmpxhg for failureThe syntax for "cmpxchg" should now look something like: cmpxchg i32* %addr, i32 42, i32 3 acquire monotonicwhere the second ordering argument gives the required semantics in the casethat no exchange takes place. It should be no stronger than the first orderingconstraint and cannot be either "release" or "acq_rel" (since no store willhave taken place).rdar://problem/15996804llvm-svn: 203559 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/atomic-2.ll

d24ab20e - Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally.

Sun, 14 Jul 2013 06:24:09 +0000

Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally.This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@$[A-Za-z0-9_]*$(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;$.*$$[A-Za-z0-9_-]*$:$ *$$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;$.*$-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;$.*$-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;$.*$-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;$.*$-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi donellvm-svn: 186280 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/atomic-2.ll

1b5ff08d - Expand PPC64 atomic load and store

Tue, 25 Dec 2012 17:22:53 +0000

Expand PPC64 atomic load and storeUse of store or load with the atomic specifier on 64-bit types wouldcause instruction-selection failures. As with the 32-bit case, thesecan use the default expansion in terms of cmp-and-swap.llvm-svn: 171072 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/atomic-2.ll

6fb0c1e4 - Convert more tests over to the new atomic instructions.

Mon, 26 Sep 2011 21:30:17 +0000

Convert more tests over to the new atomic instructions. I did not convert Atomics-32.ll and Atomics-64.ll by hand; the diff is autoupgrade output.The wmb test is gone because there isn't any way to express wmb with the new atomic instructions; if someone really needs a non-asm way to write a wmb on Alpha, a platform-specific intrisic could be added.llvm-svn: 140566 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/atomic-2.ll

4d5532a0 - FileCheck-ize a couple tests.

Mon, 18 Jul 2011 21:23:42 +0000

FileCheck-ize a couple tests.llvm-svn: 135427 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/atomic-2.ll

80ed9dc9 - rip out a ton of intrinsic modernization logic from AutoUpgrade.cpp, which is

Sat, 18 Jun 2011 06:05:24 +0000

rip out a ton of intrinsic modernization logic from AutoUpgrade.cpp, which isfor pre-2.9 bitcode files. We keep x86 unaligned loads, movnt, crc32, and thetarget indep prefetch change.As usual, updating the testsuite is a PITA.llvm-svn: 133337 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/atomic-2.ll

c8054d90 - Eliminate more uses of llvm-as and llvm-dis.

Wed, 09 Sep 2009 00:09:15 +0000

Eliminate more uses of llvm-as and llvm-dis.llvm-svn: 81293 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/atomic-2.ll