en Copyright 2015 Java http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/truncStore_and_aExtLoad.ll#28f2f662 GlobalISel: Use LLT in memory legality queriesThis enables proper lowering of non-byte sized loads. We still aren'tfaithfully preserving memory types everywhere, so the legality checksstill only consider the size. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/truncStore_and_aExtLoad.ll Wed, 09 Jun 2021 00:22:45 +0000 Matt Arsenault <Matthew.Arsenault@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/truncStore_and_aExtLoad.ll#1f559353 [MIPS GlobalISel] Select andi, ori and xoriIntroduce IntImmLeaf version of PatLeaf immZExt16 for 32-bit immediates.Change immZExt16 with imm32ZExt16 for andi, ori and xori.This keeps same behavior for SDAG and allows for GlobalISel selectImplto select 'G_CONSTANT imm' + G_AND, G_OR, G_XOR into ANDi, ORi, XORi,respectively, when 32-bit imm satisfies imm32ZExt16 predicate: zeroextending 16 low bits of imm is equal to imm.Large number of test changes comes from zero extending of small typeswhich is transformed into 'and' with bitmask in legalizer.Differential Revision:https://reviews.llvm.org/D70185 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/truncStore_and_aExtLoad.ll Fri, 15 Nov 2019 10:41:25 +0000 Petar Avramovic <Petar.Avramovic@rt-rk.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/truncStore_and_aExtLoad.ll#c2e35a6f RegAllocFast: Remove early selection loop, the spill calculation will report cost 0 anyway for free regsThe 2nd loop calculates spill costs but reports free registers as cost0 anyway, so there is little benefit from having a separate earlyloop.Surprisingly this is not NFC, as many register are marked regDisabledso the first loop often picks up later registers unnecessarily insteadof the first one available in the allocation order...Patch by Matthias Braunllvm-svn: 356499 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/truncStore_and_aExtLoad.ll Tue, 19 Mar 2019 19:01:34 +0000 Matt Arsenault <Matthew.Arsenault@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/truncStore_and_aExtLoad.ll#3e0da146 [MIPS GlobalISel] Improve selection of constantsCertain 32 bit constants can be generated with a single instructioninstead of two. Implement materialize32BitImm function for MIPS32.Differential Revision: https://reviews.llvm.org/D59369llvm-svn: 356238 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/truncStore_and_aExtLoad.ll Fri, 15 Mar 2019 07:07:50 +0000 Petar Avramovic <Petar.Avramovic@rt-rk.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/truncStore_and_aExtLoad.ll#c98b26d3 [MIPS GlobalISel] Select any extending load and truncating storeMake behavior of G_LOAD in widenScalar same as for G_ZEXTLOAD andG_SEXTLOAD. That is perform widenScalarDst to size given by the targetand avoid additional checks in common code. Targets can reorder or addadditional rules in LegalizeRuleSet for the opcode to achieve desiredbehavior.Select extending load that does not have specified type of extensioninto zero extending load.Select truncating store that stores number of bytes indicated by sizein MachineMemoperand.Differential Revision: https://reviews.llvm.org/D57454llvm-svn: 353520 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/truncStore_and_aExtLoad.ll Fri, 08 Feb 2019 14:27:23 +0000 Petar Avramovic <Petar.Avramovic@rt-rk.com>