en Copyright 2015 Java http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/struct_args.ll#1adca30c [Hexagon] Bitwise operations for insert/extract word not simplifiedChange the bit simplifier to generate REG_SEQUENCE instructions inaddition to COPY, which will handle cases of word insert/extract.llvm-svn: 276787 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/struct_args.ll Tue, 26 Jul 2016 18:30:11 +0000 Krzysztof Parzyszek <kparzysz@codeaurora.org> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/struct_args.ll#a7c5f040 [Hexagon] Split double registersllvm-svn: 250549 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/struct_args.ll Fri, 16 Oct 2015 20:38:54 +0000 Krzysztof Parzyszek <kparzysz@codeaurora.org> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/struct_args.ll#a79ac14f [opaque pointer type] Add textual IR support for explicit type parameter to load instructionEssentially the same as the GEP change in r230786.A similar migration script can be used to update test cases, though a few moretest case improvements/changes were required this time around: (r229269-r229278)import fileinputimport sysimport repat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))Reviewers: rafael, dexonsmith, grosserDifferential Revision: http://reviews.llvm.org/D7649llvm-svn: 230794 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/struct_args.ll Fri, 27 Feb 2015 21:17:42 +0000 David Blaikie <dblaikie@gmail.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/struct_args.ll#7ab68fbd Hexagon: Add V4 combine instructions and some more Def Pats for V2.llvm-svn: 174331 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/struct_args.ll Mon, 04 Feb 2013 15:52:56 +0000 Jyotsna Verma <jverma@codeaurora.org> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/struct_args.ll#91856a1f Enable all Hexagon tests.llvm-svn: 156824 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/struct_args.ll Tue, 15 May 2012 16:13:12 +0000 Sirish Pande <spande@codeaurora.org> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/struct_args.ll#1d195b9c Disable Hexagon test temporarily.There is an assert at line 558 in ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA).This assert needs to addressed for post RA scheduler. Until that assert is addressed,any passes that uses post ra scheduler will fail. So, I am temporarily disabling thehexagon tests until that fix is in.The assert is as follows: assert(!MI->isTerminator() && !MI->isLabel() && "Cannot schedule terminators or labels!");llvm-svn: 154617 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/struct_args.ll Thu, 12 Apr 2012 21:06:54 +0000 Sirish Pande <spande@codeaurora.org> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/struct_args.ll#9ca2e729 Hexagon: Fix a nasty order-of-initialization bug.Reenable the tests.llvm-svn: 146750 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/struct_args.ll Fri, 16 Dec 2011 19:08:59 +0000 Benjamin Kramer <benny.kra@googlemail.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/struct_args.ll#525ca5fc Temporarily disable Hexagon tests. They are failing on OS Xllvm-svn: 146455 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/struct_args.ll Tue, 13 Dec 2011 00:33:45 +0000 Tony Linthicum <tlinth@codeaurora.org> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/struct_args.ll#1213a7a5 Hexagon backend supportllvm-svn: 146412 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/struct_args.ll Mon, 12 Dec 2011 21:14:40 +0000 Tony Linthicum <tlinth@codeaurora.org>