Changes in half.ll

4cf18c28 - [ARM] Explicit lowering of half <-> double conversions.

Tue, 25 Jun 2019 11:24:50 +0000

[ARM] Explicit lowering of half <-> double conversions.If an FP_EXTEND or FP_ROUND isel dag node converts directly betweenf16 and f32 when the target CPU has no instruction to do it in one go,it has to be done in two steps instead, going via f32.Previously, this was done implicitly, because all such CPUs had thestorage-only implementation of f16 (i.e. the only thing you can dowith one at all is to convert it to/from f32). So isel would legalizethe f16 into an f32 as soon as it saw it, by inserting an fp16_to_fpnode (or vice versa), and then the fp_extend would already be f32->f64rather than f16->f64.But that technique can't support a target CPU which has full f16support but _not_ f64, such as some variants of Arm v8.1-M. So now weprovide custom lowering for FP_EXTEND and FP_ROUND, which checkssupport for f16 and f64 and decides on the best thing to do given thecombination of flags it gets back.Reviewers: dmgreen, samparker, SjoerdMeijerSubscribers: javed.absar, kristof.beyls, hiraditya, llvm-commitsTags: #llvmDifferential Revision: https://reviews.llvm.org/D60692llvm-svn: 364294 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/ARM/half.ll

760df47b - [ARM] Replace fp-only-sp and d16 with fp64 and d32.

Tue, 28 May 2019 16:13:20 +0000

[ARM] Replace fp-only-sp and d16 with fp64 and d32.Those two subtarget features were awkward because their semantics arereversed: each one indicates the _lack_ of support for something inthe architecture, rather than the presence. As a consequence, youdon't get the behavior you want if you combine two sets of featurebits.Each SubtargetFeature for an FP architecture version now comes in fourversions, one for each combination of those options. So you can stillsay (for example) '+vfp2' in a feature string and it will mean whatit's always meant, but there's a new string '+vfp2d16sp' meaning theversion without those extra options.A lot of this change is just mechanically replacing positive checksfor the old features with negative checks for the new ones. But onemore interesting change is that I've rearranged getFPUFeatures() sothat the main FPU feature is appended to the output list *before*rather than after the features derived from the Restriction field, sothat -fp64 and -d32 can override defaults added by the main feature.Reviewers: dmgreen, samparker, SjoerdMeijerSubscribers: srhines, javed.absar, eraman, kristof.beyls, hiraditya, zzheng, Petar.Avramovic, cfe-commits, llvm-commitsTags: #clang, #llvmDifferential Revision: https://reviews.llvm.org/D60691llvm-svn: 361845 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/ARM/half.ll

01b916e1 - [ARM] Tighten f64<->f16 conversion requirements

Wed, 12 Sep 2018 16:24:43 +0000

[ARM] Tighten f64<->f16 conversion requirementsFix missing Requires fields.Patch by Bernard Ogden (bogden)Reviewers: SjoerdMeijer, javed.absar, t.p.northover Reviewed By: t.p.northoverDifferential Revision: https://reviews.llvm.org/D51631llvm-svn: 342061 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/ARM/half.ll

b5ece527 - ARM: stop emitting blx instructions for most calls on MachO.

Tue, 10 May 2016 19:17:47 +0000

ARM: stop emitting blx instructions for most calls on MachO.I'm really not sure why we were in the first place, it's the linker's job toconvert between BL/BLX as necessary. Even worse, using BLX left Thumb callsthat could be locally resolved completely unencodable since all offsets to BLXare multiples of 4.rdar://26182344llvm-svn: 269101 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/ARM/half.ll

6402ad27 - [CodeGen] Use standard -not gnueabi- naming for f16 libcalls on Darwin.

Thu, 14 May 2015 01:00:51 +0000

[CodeGen] Use standard -not gnueabi- naming for f16 libcalls on Darwin.Other targets probably should as well. Since r237161, compiler-rt hasboth, but I don't see why anything other than gnueabi would use agnueabi naming scheme.llvm-svn: 237324 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/ARM/half.ll

a79ac14f - [opaque pointer type] Add textual IR support for explicit type parameter to load instruction

Fri, 27 Feb 2015 21:17:42 +0000

[opaque pointer type] Add textual IR support for explicit type parameter to load instructionEssentially the same as the GEP change in r230786.A similar migration script can be used to update test cases, though a few moretest case improvements/changes were required this time around: (r229269-r229278)import fileinputimport sysimport repat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace$\d+$ *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))Reviewers: rafael, dexonsmith, grosserDifferential Revision: http://reviews.llvm.org/D7649llvm-svn: 230794 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/ARM/half.ll

4e80b584 - ARM: support legalisation of "fptrunc ... to half" operations.

Fri, 18 Jul 2014 13:01:19 +0000

ARM: support legalisation of "fptrunc ... to half" operations.llvm-svn: 213373 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/ARM/half.ll

20bd0ced - CodeGen: soften f16 type by default instead of marking legal.

Fri, 18 Jul 2014 12:41:46 +0000

CodeGen: soften f16 type by default instead of marking legal.Actual support for softening f16 operations is still limited, and can be addedwhen it's needed. But Soften is much closer to being a useful thing to trythan keeping it Legal when no registers can actually hold such values.Longer term, we probably want something between Soften and Promote semanticsfor most targets, it'll be more efficient to promote the 4 basic operations tof32 than libcall them.llvm-svn: 213372 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/ARM/half.ll