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<rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/">
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    <title>Changes in fence-singlethread.ll</title>
    <description></description>
    <language>en</language>
    <copyright>Copyright 2015</copyright>
    <generator>Java</generator><item>
        <title>bb80d3e1 - Enhance synchscope representation</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/ARM/fence-singlethread.ll#bb80d3e1</link>
        <description>Enhance synchscope representation  OpenCL 2.0 introduces the notion of memory scopes in atomic operations to  global and local memory. These scopes restrict how synchronization is  achieved, which can result in improved performance.  This change extends existing notion of synchronization scopes in LLVM to  support arbitrary scopes expressed as target-specific strings, in addition to  the already defined scopes (single thread, system).  The LLVM IR and MIR syntax for expressing synchronization scopes has changed  to use *syncscope(&quot;&lt;scope&gt;&quot;)*, where &lt;scope&gt; can be &quot;singlethread&quot; (this  replaces *singlethread* keyword), or a target-specific name. As before, if  the scope is not specified, it defaults to CrossThread/System scope.  Implementation details:    - Mapping from synchronization scope name/string to synchronization scope id      is stored in LLVM context;    - CrossThread/System and SingleThread scopes are pre-defined to efficiently      check for known scopes without comparing strings;    - Synchronization scope names are stored in SYNC_SCOPE_NAMES_BLOCK in      the bitcode.Differential Revision: https://reviews.llvm.org/D21723llvm-svn: 307722

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/ARM/fence-singlethread.ll</description>
        <pubDate>Tue, 11 Jul 2017 22:23:00 +0000</pubDate>
        <dc:creator>Konstantin Zhuravlyov &lt;kzhuravl_dev@outlook.com&gt;</dc:creator>
    </item>
<item>
        <title>46e58354 - ARM: lower &quot;fence singlethread&quot; to a pure compiler barrier.</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/ARM/fence-singlethread.ll#46e58354</link>
        <description>ARM: lower &quot;fence singlethread&quot; to a pure compiler barrier.Single-threaded fences aren&apos;t required to provide any synchronization withother processing elements so there&apos;s no need for a DMB. They should still be abarrier for compiler optimizations though.llvm-svn: 300904

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/ARM/fence-singlethread.ll</description>
        <pubDate>Thu, 20 Apr 2017 21:56:52 +0000</pubDate>
        <dc:creator>Tim Northover &lt;tnorthover@apple.com&gt;</dc:creator>
    </item>
</channel>
</rss>
