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    <title>Changes in fast-isel-ext.ll</title>
    <description></description>
    <language>en</language>
    <copyright>Copyright 2015</copyright>
    <generator>Java</generator><item>
        <title>a835956b - Limit the range of processors supported by ARM fast isel to v6 or</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/ARM/fast-isel-ext.ll#a835956b</link>
        <description>Limit the range of processors supported by ARM fast isel to v6 orlater as that&apos;s all that is tested right now.Fixes PR24858.llvm-svn: 248027

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/ARM/fast-isel-ext.ll</description>
        <pubDate>Fri, 18 Sep 2015 20:08:18 +0000</pubDate>
        <dc:creator>Eric Christopher &lt;echristo@gmail.com&gt;</dc:creator>
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<item>
        <title>945a660c - Change the fast-isel-abort option from bool to int to enable &quot;levels&quot;</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/ARM/fast-isel-ext.ll#945a660c</link>
        <description>Change the fast-isel-abort option from bool to int to enable &quot;levels&quot;Summary:Currently fast-isel-abort will only abort for regular instructions,and just warn for function calls, terminators, function arguments.There is already fast-isel-abort-args but nothing for calls andterminators.This change turns the fast-isel-abort options into an integer option,so that multiple levels of strictness can be defined.This will help no being surprised when the &quot;abort&quot; option indeed doesnot abort, and enables the possibility to write test that verifiesthat no intrinsics are forgotten by fast-isel.Reviewers: resistor, echristoSubscribers: jfb, llvm-commitsDifferential Revision: http://reviews.llvm.org/D7941From: Mehdi Amini &lt;mehdi.amini@apple.com&gt;llvm-svn: 230775

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/ARM/fast-isel-ext.ll</description>
        <pubDate>Fri, 27 Feb 2015 18:32:11 +0000</pubDate>
        <dc:creator>Mehdi Amini &lt;mehdi.amini@apple.com&gt;</dc:creator>
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        <title>3fa74910 - ARM: Fast-isel register class constrain for extends.</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/ARM/fast-isel-ext.ll#3fa74910</link>
        <description>ARM: Fast-isel register class constrain for extends.Properly constrain the operand register class for instructions usedin [sz]ext expansion. Update more tests to use the verifier now thatwe&apos;re getting the register classes correct.rdar://12594152llvm-svn: 188594

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/ARM/fast-isel-ext.ll</description>
        <pubDate>Fri, 16 Aug 2013 23:37:36 +0000</pubDate>
        <dc:creator>Jim Grosbach &lt;grosbach@apple.com&gt;</dc:creator>
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        <title>d69f3ed9 - ARM: Clean up fast-isel machine verifier errors.</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/ARM/fast-isel-ext.ll#d69f3ed9</link>
        <description>ARM: Clean up fast-isel machine verifier errors.Lots of machine verifier errors result from using a plain GPR regclassfor incoming argument copies. A more restrictive rGPR class is moreappropriate since it more accurately represents what&apos;s happening, plusit lines up better with isel later on so the verifier is happier.Reduces the number of ARM fast-isel tests not running with the verifierenabled by over half.rdar://12594152llvm-svn: 188592

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/ARM/fast-isel-ext.ll</description>
        <pubDate>Fri, 16 Aug 2013 23:37:23 +0000</pubDate>
        <dc:creator>Jim Grosbach &lt;grosbach@apple.com&gt;</dc:creator>
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        <title>d24ab20e - Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally.</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/ARM/fast-isel-ext.ll#d24ab20e</link>
        <description>Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally.This update was done with the following bash script:  find test/CodeGen -name &quot;*.ll&quot; | \  while read NAME; do    echo &quot;$NAME&quot;    if ! grep -q &quot;^; *RUN: *llc.*debug&quot; $NAME; then      TEMP=`mktemp -t temp`      cp $NAME $TEMP      sed -n &quot;s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p&quot; &lt; $NAME | \      while read FUNC; do        sed -i &apos;&apos; &quot;s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g&quot; $TEMP      done      sed -i &apos;&apos; &quot;s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/&quot; $TEMP      sed -i &apos;&apos; &quot;s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/&quot; $TEMP      sed -i &apos;&apos; &quot;s/;\(.*\)-NOT-LABEL:/;\1-NOT:/&quot; $TEMP      sed -i &apos;&apos; &quot;s/;\(.*\)-DAG-LABEL:/;\1-DAG:/&quot; $TEMP      mv $TEMP $NAME    fi  donellvm-svn: 186280

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/ARM/fast-isel-ext.ll</description>
        <pubDate>Sun, 14 Jul 2013 06:24:09 +0000</pubDate>
        <dc:creator>Stephen Lin &lt;stephenwlin@gmail.com&gt;</dc:creator>
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        <title>18db1f2f - Enable FastISel on ARM for Linux and NaCl, not MCJIT</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/ARM/fast-isel-ext.ll#18db1f2f</link>
        <description>Enable FastISel on ARM for Linux and NaCl, not MCJITThis is a resubmit of r182877, which was reverted because it brokenMCJIT tests on ARM. The patch leaves MCJIT on ARM as it was before: onlyenabled for iOS. I&apos;ve CC&apos;ed people from the original review and revert.FastISel was only enabled for iOS ARM and Thumb2, this patch enables itfor ARM (not Thumb2) on Linux and NaCl, but not MCJIT.Thumb2 support needs a bit more work, mainly around register classrestrictions.The patch punts to SelectionDAG when doing TLS relocation on non-Darwintargets. I will fix this and other FastISel-to-SelectionDAG failures ina separate patch.The patch also forces FastISel to retain frame pointers: iOS alwayskeeps them for backtracking (so emitted code won&apos;t change because ofthis), but Linux was getting much worse code that was incorrect whenusing big frames (such as test-suite&apos;s lencod). I&apos;ll also fix this in alater patch, it will probably require a peephole so that FastISeldoesn&apos;t rematerialize frame pointers back-to-back.The test changes are straightforward, similar to:  http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130513/174279.htmlThey also add a vararg test that got dropped in that change.I ran all of lnt test-suite on A15 hardware with --optimize-option=-O0and all the tests pass. All the tests also pass on x86 make check-all. Ialso re-ran the check-all tests that failed on ARM, and they all seem topass.llvm-svn: 183966

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/ARM/fast-isel-ext.ll</description>
        <pubDate>Fri, 14 Jun 2013 02:49:43 +0000</pubDate>
        <dc:creator>JF Bastien &lt;jfb@google.com&gt;</dc:creator>
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        <title>06ce03d1 - ARM FastISel integer sext/zext improvements</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/ARM/fast-isel-ext.ll#06ce03d1</link>
        <description>ARM FastISel integer sext/zext improvementsMy recent ARM FastISel patch exposed this bug:  http://llvm.org/bugs/show_bug.cgi?id=16178The root cause is that it can&apos;t select integer sext/zext pre-ARMv6 andasserts out.The current integer sext/zext code doesn&apos;t handle other cases gracefullyeither, so this patch makes it handle all sext and zext from i1/i8/i16to i8/i16/i32, with and without ARMv6, both in Thumb and ARM mode. Thisshould fix the bug as well as make FastISel faster because it bails toSelectionDAG less often. See fastisel-ext.patch for this.fastisel-ext-tests.patch changes current tests to always use reg-imm ANDfor 8-bit zext instead of UXTB. This simplifies code since it issupported on ARMv4t and later, and at least on A15 both should performexactly the same (both have exec 1 uop 1, type I).2013-05-31-char-shift-crash.ll is a bitcode version of the above bug16178 repro.fast-isel-ext.ll tests all sext/zext combinations that ARM FastISelshould now handle.Note that my ARM FastISel enabling patch was reverted due to a separatefailure when dealing with MCJIT, I&apos;ll fix this second failure and thenturn FastISel on again for non-iOS ARM targets.I&apos;ve tested &quot;make check-all&quot; on my x86 box, and &quot;lnt test-suite&quot; on A15hardware.llvm-svn: 183551

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/ARM/fast-isel-ext.ll</description>
        <pubDate>Fri, 07 Jun 2013 20:10:37 +0000</pubDate>
        <dc:creator>JF Bastien &lt;jfb@google.com&gt;</dc:creator>
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