Changes in sad.ll

ed0f4415 - [AMDGPU] Divergence-driven compare operations instruction selection

Thu, 15 Jul 2021 16:43:56 +0000

[AMDGPU] Divergence-driven compare operations instruction selectionDescription: This change enables the compare operations to be selected to SALU/VALU form dependent of the SDNode divergence flag.Reviewed By: rampitecDifferential Revision: https://reviews.llvm.org/D106079 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/sad.ll

f787fe15 - [EarlyCSE] Remove unnecessary operand swap.

Fri, 11 Sep 2020 05:58:11 +0000

[EarlyCSE] Remove unnecessary operand swap.- As min/max are commutative operators, there is no need to swap operands. That breaks the convention calculating the hash value. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/sad.ll

62d8b8a2 - Fix 64-bit copy to SCC

Thu, 30 Jul 2020 11:56:06 +0000

Fix 64-bit copy to SCCFix 64-bit copy to SCC by restricting the pattern resultingin such a copy to subtargets supporting 64-bit scalar compare,and mapping the copy to S_CMP_LG_U64.Before introducing the S_CSELECT pattern with explicit SCC(0045786f146e78afee49eee053dc29ebc842fee1), there was no needfor handling 64-bit copy to SCC ($scc = COPY sreg_64).The proposed handling to read only the low bits was howeverbased on a false premise that it is only one bit that matters,while in fact the copy source might be a vector of booleans andall bits need to be considered.The practical problem of mapping the 64-bit copy to SCC is thatthe natural instruction to use (S_CMP_LG_U64) is not availableon old hardware. Fix it by restricting the problematic patternto subtargets supporting the instruction (hasScalarCompareEq64).Differential Revision: https://reviews.llvm.org/D85207 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/sad.ll

0045786f - [AMDGPU] Select s_cselect

Wed, 04 Mar 2020 14:13:08 +0000

[AMDGPU] Select s_cselectSummary:Add patterns to select s_cselect in the isel.Handle more cases of implicit SCC accesses in si-fix-sgpr-copiesto allow new patterns to work.Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, asbirlea, kerbowa, llvm-commitsTags: #llvmRe-commit D81925 with a bugfix D82370.Differential Revision: https://reviews.llvm.org/D81925Differential Revision: https://reviews.llvm.org/D82370 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/sad.ll

778351df - Revert "[AMDGPU] Enable compare operations to be selected by divergence"

Wed, 24 Jun 2020 14:27:23 +0000

Revert "[AMDGPU] Enable compare operations to be selected by divergence"This reverts commit 521ac0b5cea02f629d035f807460affbb65ae7ad.Reported to break thousands of piglit tests. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/sad.ll

521ac0b5 - [AMDGPU] Enable compare operations to be selected by divergence

Fri, 19 Jun 2020 14:51:54 +0000

[AMDGPU] Enable compare operations to be selected by divergenceSummary: Details: This patch enables SETCC to be selected to S_CMP_* if uniform and V_CMP_* if divergent.Reviewers: rampitec, arsenmReviewed By: rampitecSubscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commitsTags: #llvmDifferential Revision: https://reviews.llvm.org/D82194 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/sad.ll

6d9565d6 - Revert "[AMDGPU] Select s_cselect"

Fri, 19 Jun 2020 14:39:55 +0000

Revert "[AMDGPU] Select s_cselect"This caused some failures detected by the buildbot withexpensive checks enabled.This reverts commit 4067de569f119a81419fbf2e79d5f3307dfdda5b. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/sad.ll

4067de56 - [AMDGPU] Select s_cselect

Wed, 04 Mar 2020 14:13:08 +0000

[AMDGPU] Select s_cselectSummary:Add patterns to select s_cselect in the isel.Handle more cases of implicit SCC accesses in si-fix-sgpr-copiesto allow new patterns to work.Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, asbirlea, kerbowa, llvm-commitsTags: #llvmDifferential Revision: https://reviews.llvm.org/D81925 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/sad.ll

ab96ec41 - [AMDGPU] Precommit some test updates for D68338 "Remove dubious logic in bidirectional list scheduler"

Tue, 25 Feb 2020 14:38:57 +0000

[AMDGPU] Precommit some test updates for D68338 "Remove dubious logic in bidirectional list scheduler" List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/sad.ll

8c4a3523 - AMDGPU: Add pass to lower kernel arguments to loads

Tue, 26 Jun 2018 19:10:00 +0000

AMDGPU: Add pass to lower kernel arguments to loadsThis replaces most argument uses with loads, but fornow not all.The code in SelectionDAG for calling convention loweringis actively harmful for amdgpu_kernel. It attempts tosplit the argument types into register legal types, whichresults in low quality code for arbitary types. Sinceall kernel arguments are passed in memory, we just want theraw types.I've tried a couple of methods of mitigating this in SelectionDAG,but it's easier to just bypass this problem alltogether. It'spossible to hack around the problem in the initial lowering,but the real problem is the DAG then expects to be able to useCopyToReg/CopyFromReg for uses of the arguments outside the block.Exposing the argument loads in the IR also has the advantagethat the LoadStoreVectorizer can merge them.I'm not sure the best approach to dealing with the IRargument list is. The patch as-is just leaves the IR argumentsin place, so all the existing code will still compute the samekernarg size and pointlessly lowers the arguments.Arguably the frontend should emit kernels with an empty argumentlist in the first place. Alternatively a dummy array could beinserted as a single argument just to reserve space.This does have some disadvantages. Local pointer kernel arguments canno longer have AssertZext placed on them as the equivalent !rangemetadata is not valid on pointer typed loads. This is mostly badfor SI which needs to know about the known bits in order to use theDS instruction offset, so in this case this is not done.More importantly, this skips noalias arguments since this passdoes not yet convert this to the equivalent !alias.scope and !noaliasmetadata. Producing this metadata correctly seems to be tricky,although this logically is the same as inlining into a function whichdoesn't exist. Additionally, exposing these loads to the vectorizermay result in degraded aliasing information if a pointer load ismerged with another argument load.I'm also not entirely sure this is preserving the current cloverABI, although I would greatly prefer if it would stop wideningarguments and match the HSA ABI. As-is I think it is extending< 4-byte arguments to 4-bytes but doesn't align them to 4-bytes.llvm-svn: 335650 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/sad.ll

2a22c5de - [AMDGPU] Switch to the new addr space mapping by default

Fri, 02 Feb 2018 16:07:16 +0000

[AMDGPU] Switch to the new addr space mapping by defaultThis requires corresponding clang change.Differential Revision: https://reviews.llvm.org/D40955llvm-svn: 324101 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/sad.ll

8728c5f2 - AMDGPU: Cleanup subtarget features

Mon, 07 Aug 2017 14:58:04 +0000

AMDGPU: Cleanup subtarget featuresTry to avoid mutually exclusive features. Don't usea real default GPU, and use a fake "generic". The goalis to make it easier to see which set of features areincompatible between feature strings.Most of the test changes are due to random scheduling changesfrom not having a default fullspeed model.llvm-svn: 310258 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/sad.ll

9aa45f04 - AMDGPU: Add macro fusion schedule DAG mutation

Thu, 06 Jul 2017 20:57:05 +0000

AMDGPU: Add macro fusion schedule DAG mutationTry to increase opportunities to shrink vcc uses.llvm-svn: 307313 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/sad.ll

3dbeefa9 - AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel

Tue, 21 Mar 2017 21:39:51 +0000

AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernelCurrently the default C calling convention functions are treatedthe same as compute kernels. Make this explicit so the defaultcalling convention can be changed to a non-kernel.Converted with perl -pi -e 's/define void/define amdgpu_kernel void/'on the relevant test directories (and undoing in one place that actuallywanted a non-kernel).llvm-svn: 298444 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/sad.ll

0a1a7b6b - Revert "AMDGPU: Enable ConstrainCopy DAG mutation"

Thu, 17 Nov 2016 16:41:49 +0000

Revert "AMDGPU: Enable ConstrainCopy DAG mutation"This reverts commit r287146.This breaks few conformance tests.llvm-svn: 287233 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/sad.ll

3b36bb1d - AMDGPU: Enable ConstrainCopy DAG mutation

Wed, 16 Nov 2016 20:35:23 +0000

AMDGPU: Enable ConstrainCopy DAG mutationThis fixes a probably unintended divergence from the defaultscheduler behavior.llvm-svn: 287146 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/sad.ll

0d23ebe8 - AMDGPU/SI: Implement a custom MachineSchedStrategy

Mon, 29 Aug 2016 19:42:52 +0000

AMDGPU/SI: Implement a custom MachineSchedStrategySummary:GCNSchedStrategy re-uses most of GenericScheduler, it's just usesa different method to compute the excess and critical registerpressure limits.It's not enabled by default, to enable it you need to pass -misched=gcnto llc.Shader DB stats:32464 shaders in 17874 testsTotals:SGPRS: 1542846 -> 1643125 (6.50 %)VGPRS: 1005595 -> 904653 (-10.04 %)Spilled SGPRs: 29929 -> 27745 (-7.30 %)Spilled VGPRs: 334 -> 352 (5.39 %)Scratch VGPRs: 1612 -> 1624 (0.74 %) dwords per threadCode Size: 36688188 -> 37034900 (0.95 %) bytesLDS: 1913 -> 1913 (0.00 %) blocksMax Waves: 254101 -> 265125 (4.34 %)Wait states: 0 -> 0 (0.00 %)Totals from affected shaders:SGPRS: 1338220 -> 1438499 (7.49 %)VGPRS: 886221 -> 785279 (-11.39 %)Spilled SGPRs: 29869 -> 27685 (-7.31 %)Spilled VGPRs: 334 -> 352 (5.39 %)Scratch VGPRs: 1612 -> 1624 (0.74 %) dwords per threadCode Size: 34315716 -> 34662428 (1.01 %) bytesLDS: 1551 -> 1551 (0.00 %) blocksMax Waves: 188127 -> 199151 (5.86 %)Wait states: 0 -> 0 (0.00 %)Reviewers: arsenm, mareko, nhaehnle, MatzeB, atrickSubscribers: arsenm, kzhuravl, llvm-commitsDifferential Revision: https://reviews.llvm.org/D23688llvm-svn: 279995 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/sad.ll

1041a646 - AMDGPU : Add V_SAD_U32 instruction pattern.

Wed, 24 Aug 2016 14:59:47 +0000

AMDGPU : Add V_SAD_U32 instruction pattern.Differential Revision: http://reviews.llvm.org/D23069llvm-svn: 279629 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/sad.ll