Changes in llvm.amdgcn.struct.tbuffer.store.d16.ll

3eb2281b - [AMDGPU] Aggressively fold immediates in SIFoldOperands

Mon, 16 May 2022 14:48:11 +0000

[AMDGPU] Aggressively fold immediates in SIFoldOperandsPreviously SIFoldOperands::foldInstOperand would only fold anon-inlinable immediate into a single user, so as not to increase codesize by adding the same 32-bit literal operand to many instructions.This patch removes that restriction, so that a non-inlinable immediatewill be folded into any number of users. The rationale is:- It reduces the number of registers used for holding constant values, which might increase occupancy. (On the other hand, many of these registers are SGPRs which no longer affect occupancy on GFX10+.)- It reduces ALU stalls between the instruction that loads a constant into a register, and the instruction that uses it.- The above benefits are expected to outweigh any increase in code size.Differential Revision: https://reviews.llvm.org/D114643 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll

f510045d - [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC.

Fri, 14 Jan 2022 11:03:21 +0000

[CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC.Take advantage of D117117 to simplify all {{\[}} to [ and {{\]}} to ].Differential Revision: https://reviews.llvm.org/D117298 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll

b4706309 - [NFC] Removed unused prefixes from CodeGen/AMDGPU

Wed, 06 Jan 2021 04:23:39 +0000

[NFC] Removed unused prefixes from CodeGen/AMDGPUAll the 'l'-starting tests.Differential Revision: https://reviews.llvm.org/D94151 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll

833b3b0d - [AMDGPU] Add v3f16/v3i16 support to SDag

Thu, 23 Jul 2020 14:59:00 +0000

[AMDGPU] Add v3f16/v3i16 support to SDagFix lowering and instruction selection for v3x16 typesand enable InstCombine to emit them.This patch only implements it for the selection dag.GlobalISel tests in GlobalISel/llvm.amdgcn.image.load.1d.d16.ll andGlobalISel/llvm.amdgcn.image.store.2d.d16.ll still don't work.Differential Revision: https://reviews.llvm.org/D84420 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll

6b894892 - [AMDGPU][MC] Added support of SP3 syntax for MTBUF format modifier

Fri, 24 Jul 2020 13:39:42 +0000

[AMDGPU][MC] Added support of SP3 syntax for MTBUF format modifierCurrently supported LLVM MTBUF syntax is shown below. It is not compatible with SP3. op dst, addr, rsrc, FORMAT, soffsetThis change adds support for SP3 syntax: op dst, addr, rsrc, soffset SP3FORMATIn addition to being compatible with SP3, this syntax allows using symbolic names for data, numeric and unified formats. Below is a list of added syntax variants.format:format:[,]format:[,]format:[]format:[]format:[]The last syntax variant is supported for GFX10 only.See llvm bug 37738Reviewers: arsenm, rampitec, vpykhtinDifferential Revision: https://reviews.llvm.org/D84026 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll

692560dc - [AMDGPU] gfx1010 MIMG implementation

Wed, 01 May 2019 16:32:58 +0000

[AMDGPU] gfx1010 MIMG implementationDifferential Revision: https://reviews.llvm.org/D61339llvm-svn: 359698 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll

35484c9d - [AMDGPU] New tbuffer intrinsics

Tue, 21 Aug 2018 11:06:05 +0000

[AMDGPU] New tbuffer intrinsicsSummary:This commit adds new intrinsics llvm.amdgcn.raw.tbuffer.load llvm.amdgcn.struct.tbuffer.load llvm.amdgcn.raw.tbuffer.store llvm.amdgcn.struct.tbuffer.storewith the following changes from the llvm.amdgcn.tbuffer.* intrinsics:* there are separate raw and struct versions: raw does not have an index arg and sets idxen=0 in the instruction, and struct always sets idxen=1 in the instruction even if the index is 0, to allow for the fact that gfx9 does bounds checking differently depending on whether idxen is set;* there is a combined format arg (dfmt+nfmt)* there is a combined cachepolicy arg (glc+slc)* there are now only two offset args: one for the offset that is included in bounds checking and swizzling, to be split between the instruction's voffset and immoffset fields, and one for the offset that is excluded from bounds checking and swizzling, to go into the instruction's soffset field.The AMDISD::TBUFFER_* SD nodes always have an index operand, all threeoffset operands, combined format operand, combined cachepolicy operand,and an extra idxen operand.The tbuffer pseudo- and real instructions now also have a combinedformat operand.The obsolescent llvm.amdgcn.tbuffer.* and llvm.SI.tbuffer.storeintrinsics continue to work.V2: Separate raw and struct intrinsics.V3: Moved extract_glc and extract_slc defs to a more sensible place.V4: Rebased on D49995.V5: Only two separate offset args instead of three.V6: Pseudo- and real instructions have joint format operand.V7: Restored optionality of dfmt and nfmt in assembler.V8: Addressed minor review comments.Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commitsDifferential Revision: https://reviews.llvm.org/D49026Change-Id: If22ad77e349fac3a5d2f72dda53c010377d470d4llvm-svn: 340268 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll