Changes in llvm.amdgcn.buffer.store.format.d16.ll

3eb2281b - [AMDGPU] Aggressively fold immediates in SIFoldOperands

Mon, 16 May 2022 14:48:11 +0000

[AMDGPU] Aggressively fold immediates in SIFoldOperandsPreviously SIFoldOperands::foldInstOperand would only fold anon-inlinable immediate into a single user, so as not to increase codesize by adding the same 32-bit literal operand to many instructions.This patch removes that restriction, so that a non-inlinable immediatewill be folded into any number of users. The rationale is:- It reduces the number of registers used for holding constant values, which might increase occupancy. (On the other hand, many of these registers are SGPRs which no longer affect occupancy on GFX10+.)- It reduces ALU stalls between the instruction that loads a constant into a register, and the instruction that uses it.- The above benefits are expected to outweigh any increase in code size.Differential Revision: https://reviews.llvm.org/D114643 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.d16.ll

f510045d - [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC.

Fri, 14 Jan 2022 11:03:21 +0000

[CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC.Take advantage of D117117 to simplify all {{\[}} to [ and {{\]}} to ].Differential Revision: https://reviews.llvm.org/D117298 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.d16.ll

b4706309 - [NFC] Removed unused prefixes from CodeGen/AMDGPU

Wed, 06 Jan 2021 04:23:39 +0000

[NFC] Removed unused prefixes from CodeGen/AMDGPUAll the 'l'-starting tests.Differential Revision: https://reviews.llvm.org/D94151 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.d16.ll

136f4989 - AMDGPU: Explicitly use SelectionDAG in legacy intrinsic tests

Thu, 30 Jul 2020 02:50:02 +0000

AMDGPU: Explicitly use SelectionDAG in legacy intrinsic testsGlobalISel will probably not support the legacy buffer intrinsics, sodon't fail when the default is switched. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.d16.ll

833b3b0d - [AMDGPU] Add v3f16/v3i16 support to SDag

Thu, 23 Jul 2020 14:59:00 +0000

[AMDGPU] Add v3f16/v3i16 support to SDagFix lowering and instruction selection for v3x16 typesand enable InstCombine to emit them.This patch only implements it for the selection dag.GlobalISel tests in GlobalISel/llvm.amdgcn.image.load.1d.d16.ll andGlobalISel/llvm.amdgcn.image.store.2d.d16.ll still don't work.Differential Revision: https://reviews.llvm.org/D84420 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.d16.ll

8c4a3523 - AMDGPU: Add pass to lower kernel arguments to loads

Tue, 26 Jun 2018 19:10:00 +0000

AMDGPU: Add pass to lower kernel arguments to loadsThis replaces most argument uses with loads, but fornow not all.The code in SelectionDAG for calling convention loweringis actively harmful for amdgpu_kernel. It attempts tosplit the argument types into register legal types, whichresults in low quality code for arbitary types. Sinceall kernel arguments are passed in memory, we just want theraw types.I've tried a couple of methods of mitigating this in SelectionDAG,but it's easier to just bypass this problem alltogether. It'spossible to hack around the problem in the initial lowering,but the real problem is the DAG then expects to be able to useCopyToReg/CopyFromReg for uses of the arguments outside the block.Exposing the argument loads in the IR also has the advantagethat the LoadStoreVectorizer can merge them.I'm not sure the best approach to dealing with the IRargument list is. The patch as-is just leaves the IR argumentsin place, so all the existing code will still compute the samekernarg size and pointlessly lowers the arguments.Arguably the frontend should emit kernels with an empty argumentlist in the first place. Alternatively a dummy array could beinserted as a single argument just to reserve space.This does have some disadvantages. Local pointer kernel arguments canno longer have AssertZext placed on them as the equivalent !rangemetadata is not valid on pointer typed loads. This is mostly badfor SI which needs to know about the known bits in order to use theDS instruction offset, so in this case this is not done.More importantly, this skips noalias arguments since this passdoes not yet convert this to the equivalent !alias.scope and !noaliasmetadata. Producing this metadata correctly seems to be tricky,although this logically is the same as inlining into a function whichdoesn't exist. Additionally, exposing these loads to the vectorizermay result in degraded aliasing information if a pointer load ismerged with another argument load.I'm also not entirely sure this is preserving the current cloverABI, although I would greatly prefer if it would stop wideningarguments and match the HSA ABI. As-is I think it is extending< 4-byte arguments to 4-bytes but doesn't align them to 4-bytes.llvm-svn: 335650 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.d16.ll

02dc7e19 - AMDGPU: Make v4i16/v4f16 legal

Fri, 15 Jun 2018 15:15:46 +0000

AMDGPU: Make v4i16/v4f16 legalSome image loads return these, and it's awkward workingaround them not being legal.llvm-svn: 334835 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.d16.ll

90083d30 - AMDGPU: Try a lot harder to emit scalar loads

Thu, 07 Jun 2018 09:54:49 +0000

AMDGPU: Try a lot harder to emit scalar loadsThis has two main components. First, widenwiden short constant loads in DAG when they havethe correct alignment. This is already done a bit inAMDGPUCodeGenPrepare, since that has access toDivergenceAnalysis. This can't help kernarg loadscreated in the DAG. Start to use DAG divergence analysisto help this case.The second part is to avoid kernel argument loweringbreaking the alignment of short vector elements becausecalling convention lowering wants to split everythinginto legal register types.When loading a split type, load the nearest 4-byte alignedsegment and shift to get the desired bits. This extraload of the earlier argument piece ends up merging,and the bit extract hopefully folds out.There are a number of improvements and regressions withthis, but I think as-is this is a better compromise betweenseveral of the worst parts of SelectionDAG.Particularly when i16 is legal, this produces worse codefor i8 and i16 element vector kernel arguments. This ispartially due to the very weak load merging the DAG does.It only looks for fairly specific combines between pairsof loads which no longer appear. In particular thiscauses v4i16 loads to be split into 2 components whenpreviously the two halves were merged.Worse, because of the newly introduced shifts, thereis a lot more unnecessary vector packing and unpacking codeemitted. At least some of this is due to reportingfalse for isTypeDesirableForOp for i16 as a workaround forthe lack of divergence information in the DAG. The caseswhere this happens it doesn't actually matter, but therelevant code in SimplifyDemandedBits doens't have the contextto know to ignore this.The use of the scalar cache is probably more importantthan the mess of mostly scalar instructions doing this packingand unpacking. Future work can fix this, possibly by making betteruse of the new DAG divergence information for controlling promotiondecisions, or adding another version of shift + trunc + shiftcombines that doesn't only know about the used types.llvm-svn: 334180 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.d16.ll

72a9f52c - AMDGPU: Switch some half using-tests to use amdhsa

Fri, 01 Jun 2018 07:06:03 +0000

AMDGPU: Switch some half using-tests to use amdhsaThe default clover ABI weirdly promotes half to float,which should probably be fixed.llvm-svn: 333730 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.d16.ll

1349a04e - AMDGPU: Make v2i16/v2f16 legal on VI

Tue, 22 May 2018 06:32:10 +0000

AMDGPU: Make v2i16/v2f16 legal on VIThis usually results in better code. Fixes usinginline asm with short2, and also fixes having a differentABI for function parameters between VI and gfx9.Partially cleans up the mess used for lowering of the d16operations. Making v4f16 legal will help clean this up more,but this requires additional work.llvm-svn: 332953 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.d16.ll

c078ca92 - [AMDGPU] Remove non-temporal flag from argument loads

Wed, 14 Feb 2018 18:05:14 +0000

[AMDGPU] Remove non-temporal flag from argument loadsKernel arguments likely read by all workitems and should not bypasscache. Fixes performance hit in sub-dword argument loads.Differential Revision: https://reviews.llvm.org/D43249llvm-svn: 325146 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.d16.ll

29fcf883 - AMDGPU/SI: Adjust the encoding family for D16 buffer instructions when the target has UnpackedD16VMem feature.

Thu, 01 Feb 2018 18:41:33 +0000

AMDGPU/SI: Adjust the encoding family for D16 buffer instructions when the target has UnpackedD16VMem feature.Reviewers: Matt and BrianDifferential Revision: https://reviews.llvm.org/D42548llvm-svn: 323988 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.d16.ll

44dfa1de - AMDGPU/SI: Add d16 support for buffer intrinsics.

Fri, 12 Jan 2018 21:12:19 +0000

AMDGPU/SI: Add d16 support for buffer intrinsics.Differential Revision: https://reviews.llvm.org/D38906Reviewers: Matt and Brian.llvm-svn: 322402 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.d16.ll