en Copyright 2015 Java http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll#f6462a26 [AMDGPU] Split unaligned 4 DWORD DS operationsSimilarly to 3 DWORD operations it is better for performanceto split unlaligned operations as long a these are at leastDWORD alignmened. Performance data:```Using platform: AMD Accelerated Parallel ProcessingUsing device: gfx900:xnack-ds_write_b128 aligned by 16: 4.9 secds_write2_b64 aligned by 16: 5.1 secds_write2_b32 * 2 aligned by 16: 5.5 secds_write_b128 aligned by 1: 8.1 secds_write2_b64 aligned by 1: 8.7 secds_write2_b32 * 2 aligned by 1: 14.0 secds_write_b128 aligned by 2: 8.1 secds_write2_b64 aligned by 2: 8.7 secds_write2_b32 * 2 aligned by 2: 14.0 secds_write_b128 aligned by 4: 5.6 secds_write2_b64 aligned by 4: 8.7 secds_write2_b32 * 2 aligned by 4: 5.6 secds_write_b128 aligned by 8: 5.6 secds_write2_b64 aligned by 8: 5.1 secds_write2_b32 * 2 aligned by 8: 5.6 secds_read_b128 aligned by 16: 3.8 secds_read2_b64 aligned by 16: 3.8 secds_read2_b32 * 2 aligned by 16: 4.0 secds_read_b128 aligned by 1: 4.6 secds_read2_b64 aligned by 1: 8.1 secds_read2_b32 * 2 aligned by 1: 14.0 secds_read_b128 aligned by 2: 4.6 secds_read2_b64 aligned by 2: 8.1 secds_read2_b32 * 2 aligned by 2: 14.0 secds_read_b128 aligned by 4: 4.6 secds_read2_b64 aligned by 4: 8.1 secds_read2_b32 * 2 aligned by 4: 4.0 secds_read_b128 aligned by 8: 4.6 secds_read2_b64 aligned by 8: 3.8 secds_read2_b32 * 2 aligned by 8: 4.0 secUsing platform: AMD Accelerated Parallel ProcessingUsing device: gfx1030ds_write_b128 aligned by 16: 6.2 secds_write2_b64 aligned by 16: 7.1 secds_write2_b32 * 2 aligned by 16: 7.6 secds_write_b128 aligned by 1: 24.1 secds_write2_b64 aligned by 1: 25.2 secds_write2_b32 * 2 aligned by 1: 43.7 secds_write_b128 aligned by 2: 24.1 secds_write2_b64 aligned by 2: 25.1 secds_write2_b32 * 2 aligned by 2: 43.7 secds_write_b128 aligned by 4: 14.4 secds_write2_b64 aligned by 4: 25.1 secds_write2_b32 * 2 aligned by 4: 7.6 secds_write_b128 aligned by 8: 14.4 secds_write2_b64 aligned by 8: 7.1 secds_write2_b32 * 2 aligned by 8: 7.6 secds_read_b128 aligned by 16: 6.2 secds_read2_b64 aligned by 16: 6.3 secds_read2_b32 * 2 aligned by 16: 7.5 secds_read_b128 aligned by 1: 12.5 secds_read2_b64 aligned by 1: 24.0 secds_read2_b32 * 2 aligned by 1: 43.6 secds_read_b128 aligned by 2: 12.5 secds_read2_b64 aligned by 2: 24.0 secds_read2_b32 * 2 aligned by 2: 43.6 secds_read_b128 aligned by 4: 12.5 secds_read2_b64 aligned by 4: 24.0 secds_read2_b32 * 2 aligned by 4: 7.5 secds_read_b128 aligned by 8: 12.5 secds_read2_b64 aligned by 8: 6.3 secds_read2_b32 * 2 aligned by 8: 7.5 sec```Differential Revision: https://reviews.llvm.org/D123634 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll Mon, 11 Apr 2022 22:25:11 +0000 Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll#3870b360 [AMDGPU] Split unaligned 3 DWORD DS operationsI have written a minitest to check the performance. Overallthe benefit of aligned b96 operations on data which is notknown but happens to be aligned is small, while performancehit of using b96 operations on a really unaligned memory ishigh.The only exception is when data is not aligned even by 4, itis better to use b96 in this case.Here is the test output on Vega and Navi:```Using platform: AMD Accelerated Parallel ProcessingUsing device: gfx900:xnack-ds_write_b96 aligned: 3.4 secds_write_b32 + ds_write_b64 aligned: 4.5 secds_write_b32 * 3 aligned: 4.8 secds_write_b96 misaligned by 1: 4.8 secds_write_b32 + ds_write_b64 misaligned by 1: 7.2 secds_write_b32 * 3 misaligned by 1: 10.0 secds_write_b96 misaligned by 2: 4.8 secds_write_b32 + ds_write_b64 misaligned by 2: 7.2 secds_write_b32 * 3 misaligned by 2: 10.1 secds_write_b96 misaligned by 4: 4.8 secds_write_b32 + ds_write_b64 misaligned by 4: 4.2 secds_write_b32 * 3 misaligned by 4: 4.9 secds_write_b96 misaligned by 8: 4.8 secds_write_b32 + ds_write_b64 misaligned by 8: 4.6 secds_write_b32 * 3 misaligned by 8: 4.9 secds_read_b96 aligned: 3.3 secds_read_b32 + ds_read_b64 aligned: 4.9 secds_read_b32 * 3 aligned: 2.6 secds_read_b96 misaligned by 1: 4.1 secds_read_b32 + ds_read_b64 misaligned by 1: 7.2 secds_read_b32 * 3 misaligned by 1: 10.1 secds_read_b96 misaligned by 2: 4.1 secds_read_b32 + ds_read_b64 misaligned by 2: 7.2 secds_read_b32 * 3 misaligned by 2: 10.1 secds_read_b96 misaligned by 4: 4.1 secds_read_b32 + ds_read_b64 misaligned by 4: 2.6 secds_read_b32 * 3 misaligned by 4: 2.6 secds_read_b96 misaligned by 8: 4.1 secds_read_b32 + ds_read_b64 misaligned by 8: 4.9 secds_read_b32 * 3 misaligned by 8: 2.6 secUsing platform: AMD Accelerated Parallel ProcessingUsing device: gfx1030ds_write_b96 aligned: 4.1 secds_write_b32 + ds_write_b64 aligned: 13.0 secds_write_b32 * 3 aligned: 4.5 secds_write_b96 misaligned by 1: 12.5 secds_write_b32 + ds_write_b64 misaligned by 1: 22.0 secds_write_b32 * 3 misaligned by 1: 31.5 secds_write_b96 misaligned by 2: 12.4 secds_write_b32 + ds_write_b64 misaligned by 2: 22.0 secds_write_b32 * 3 misaligned by 2: 31.5 secds_write_b96 misaligned by 4: 12.4 secds_write_b32 + ds_write_b64 misaligned by 4: 4.0 secds_write_b32 * 3 misaligned by 4: 4.5 secds_write_b96 misaligned by 8: 12.4 secds_write_b32 + ds_write_b64 misaligned by 8: 13.0 secds_write_b32 * 3 misaligned by 8: 4.5 secds_read_b96 aligned: 3.8 secds_read_b32 + ds_read_b64 aligned: 12.8 secds_read_b32 * 3 aligned: 4.4 secds_read_b96 misaligned by 1: 10.9 secds_read_b32 + ds_read_b64 misaligned by 1: 21.8 secds_read_b32 * 3 misaligned by 1: 31.5 secds_read_b96 misaligned by 2: 10.9 secds_read_b32 + ds_read_b64 misaligned by 2: 21.9 secds_read_b32 * 3 misaligned by 2: 31.5 secds_read_b96 misaligned by 4: 10.9 secds_read_b32 + ds_read_b64 misaligned by 4: 3.8 secds_read_b32 * 3 misaligned by 4: 4.5 secds_read_b96 misaligned by 8: 10.9 secds_read_b32 + ds_read_b64 misaligned by 8: 12.8 secds_read_b32 * 3 misaligned by 8: 4.5 sec```Fixes: SWDEV-330802Differential Revision: https://reviews.llvm.org/D123524 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll Mon, 11 Apr 2022 17:13:31 +0000 Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll#ac64995c [AMDGPU] Only use ds_read/write_b128 for alignment >= 16PS: Submitting on behalf of Jay.Reviewed By: rampitecDifferential Revision: https://reviews.llvm.org/D100008 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll Thu, 08 Apr 2021 02:41:42 +0000 hsmahesha <mahesha.comp@gmail.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll#0c7cce54 [AMDGPU] Resolve issues when picking between ds_read/write and ds_read2/write2Both ds_read_b128 and ds_read2_b64 are valid for 128bit 16-byte alignedloads but the one that will be selected is determined either by the order intablegen or by the AddedComplexity attribute. Currently ds_read_b128 haspriority.While ds_read2_b64 has lower alignment requirements, we cannot alwaysrestrict ds_read_b128 to 16-byte alignment because of unaligned-access-modeoption. This was causing ds_read_b128 to be selected for 8-byte alignedloads regardles of chosen access mode.To resolve this we use two patterns for selecting ds_read_b128. Onerequires alignment of 16-byte and the other requiresunaligned-access-mode option.Same goes for ds_write2_b64 and ds_write_b128.Differential Revision: https://reviews.llvm.org/D92767 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll Thu, 10 Dec 2020 11:40:49 +0000 Mirko Brkusanin <Mirko.Brkusanin@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll#ae36c02a [AMDGPU] Set DS alignment requirements to be more strictAlignment requirements for ds_read/write_b96/b128 for gfx9 and onward arenow the same as for other GCN subtargets. This way we can avoid anyunintentional use of these instructions on systems that do not support dwordalignment and instead require natural alignment.This also makes 'SH_MEM_CONFIG.alignment_mode == STRICT' the default.Differential Revision: https://reviews.llvm.org/D87821 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll Fri, 18 Sep 2020 13:19:54 +0000 Mirko Brkusanin <Mirko.Brkusanin@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll#43af2a6f [AMDGPU] Workaround for LDS Misalignment bug on GFX10Add subtarget feature check to avoid using ds_read/write_b96/128 with toolow alignment if a bug is present on that specific hardware.Add this "feature" to GFX 10.1.1 as it is also affected.Add global-isel test. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll Wed, 09 Sep 2020 09:28:36 +0000 Mirko Brkusanin <Mirko.Brkusanin@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll#0654ff70 [AMDGPU] Use ds_read/write_b96/b128 when possible for SDagDo not break down local loads and stores so ds_read/write_b96/b128 inISelLowering can be selected on subtargets that support them and if alignrequirements allow them.Differential Revision: https://reviews.llvm.org/D84403 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll Fri, 21 Aug 2020 09:51:06 +0000 Mirko Brkusanin <Mirko.Brkusanin@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll#c43e67bf [AMDGPU] gfx1011/gfx1012 targetsDifferential Revision: https://reviews.llvm.org/D63307llvm-svn: 363344 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll Fri, 14 Jun 2019 00:33:31 +0000 Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll#a224f68a [AMDGPU] gfx1010 DS implementationDifferential Revision: https://reviews.llvm.org/D61332llvm-svn: 359696 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll Wed, 01 May 2019 16:11:11 +0000 Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com>