en Copyright 2015 Java http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/insert-subvector-unused-scratch.ll#da067ed5 [AMDGPU] Set most sched model resource's BufferSize to oneUsing a BufferSize of one for memory ProcResources will result in betterILP since it more accurately models the dependencies between memory opsand their consumers on an in-order processor. After this change, thescheduler will treat the data edges from loads as blocking so thatstalls are guaranteed when waiting for data to be retreaved from memory.Since we don't actually track waitcnt here, this should do a better jobat modeling their behavior.Practically, this means that the scheduler will trigger the 'STALL'heuristic more often.This type of change needs to be evaluated experimentally. Preliminaryresults are positive.Fixes: SWDEV-282962Reviewed By: rampitecDifferential Revision: https://reviews.llvm.org/D114777 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/insert-subvector-unused-scratch.ll Wed, 10 Nov 2021 17:59:31 +0000 Austin Kerbow <Austin.Kerbow@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/insert-subvector-unused-scratch.ll#0654ff70 [AMDGPU] Use ds_read/write_b96/b128 when possible for SDagDo not break down local loads and stores so ds_read/write_b96/b128 inISelLowering can be selected on subtargets that support them and if alignrequirements allow them.Differential Revision: https://reviews.llvm.org/D84403 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/insert-subvector-unused-scratch.ll Fri, 21 Aug 2020 09:51:06 +0000 Mirko Brkusanin <Mirko.Brkusanin@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/insert-subvector-unused-scratch.ll#f68cc2a7 AMDGPU: Use 128-bit DS operations by default List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/insert-subvector-unused-scratch.ll Wed, 01 Apr 2020 20:46:10 +0000 Matt Arsenault <Matthew.Arsenault@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/insert-subvector-unused-scratch.ll#b777e551 [MachineScheduler] Reduce reordering due to mem op clusteringSummary:Mem op clustering adds a weak edge in the DAG between two loads orstores that should be clustered, but the direction of this edge ispretty arbitrary (it depends on the sort order of MemOpInfo, whichrepresents the operands of a load or store). This often means that twoloads or stores will get reordered even if they would naturally havebeen scheduled together anyway, which leads to test case churn and goesagainst the scheduler's "do no harm" philosophy.The fix makes sure that the direction of the edge always matches theoriginal code order of the instructions.Reviewers: atrick, MatzeB, arsenm, rampitec, t.p.northoverSubscribers: jvesely, wdng, nhaehnle, kristof.beyls, hiraditya, javed.absar, arphaman, llvm-commitsTags: #llvmDifferential Revision: https://reviews.llvm.org/D72706 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/insert-subvector-unused-scratch.ll Tue, 14 Jan 2020 15:40:52 +0000 Jay Foad <jay.foad@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/insert-subvector-unused-scratch.ll#5816889c [AMDGPU] Custom lower INSERT_SUBVECTOR v3, v4, v5, v8Summary:Since the changes to introduce vec3 and vec5, INSERT_VECTOR for thesesizes has been marked "expand", which made LegalizeDAG lower it to loadsand stores via a stack slot. The code got optimized a bit later, but thenow-unused stack slot was never deleted.This commit avoids that problem by custom lowering INSERT_SUBVECTOR intoan EXTRACT_VECTOR_ELT and INSERT_VECTOR_ELT for each element in thesubvector to insert.V2: Addressed review comments re test.Differential Revision: https://reviews.llvm.org/D63160Change-Id: I9e3c13e36f68cfa3431bb9814851cc1f673274e1llvm-svn: 365148 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/insert-subvector-unused-scratch.ll Thu, 04 Jul 2019 17:38:24 +0000 Tim Renouf <tpr.llvm@botech.co.uk>