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    <title>Changes in hsa.ll</title>
    <description></description>
    <language>en</language>
    <copyright>Copyright 2015</copyright>
    <generator>Java</generator><item>
        <title>8fc8bf59 - [AMDGPU] Add GFX11 test coverage sharing checks with GFX10</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll#8fc8bf59</link>
        <description>[AMDGPU] Add GFX11 test coverage sharing checks with GFX10

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll</description>
        <pubDate>Fri, 08 Jul 2022 10:44:23 +0000</pubDate>
        <dc:creator>Jay Foad &lt;jay.foad@amd.com&gt;</dc:creator>
    </item>
<item>
        <title>a9854045 - [test] Change -t to --syms and -s to -S for llvm-readobj RUN lines</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll#a9854045</link>
        <description>[test] Change -t to --syms and -s to -S for llvm-readobj RUN lines-s and -t will be changed to improve consistency with llvm-readelf.The inconsistency issue regularly contributes to confusion using the two tools.

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll</description>
        <pubDate>Tue, 29 Jun 2021 18:50:31 +0000</pubDate>
        <dc:creator>Fangrui Song &lt;i@maskray.me&gt;</dc:creator>
    </item>
<item>
        <title>f4ace637 - AMDGPU: Add target id and code object v4 support</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll#f4ace637</link>
        <description>AMDGPU: Add target id and code object v4 support  - Add target id support (https://clang.llvm.org/docs/ClangOffloadBundler.html#target-id)  - Add code object v4 support (https://llvm.org/docs/AMDGPUUsage.html#elf-code-object)    - Add kernarg_size to kernel descriptor    - Change trap handler ABI to no longer move queue pointer into s[0:1]  - Cleanup ELF definitions    - Add V2, V3, V4 suffixes to make a clear distinction for code object version    - Consolidate note namesDifferential Revision: https://reviews.llvm.org/D95638

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll</description>
        <pubDate>Wed, 24 Mar 2021 15:52:10 +0000</pubDate>
        <dc:creator>Konstantin Zhuravlyov &lt;kzhuravl_dev@outlook.com&gt;</dc:creator>
    </item>
<item>
        <title>d2e52eec - AMDGPU: Select global saddr mode from SGPR pointer</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll#d2e52eec</link>
        <description>AMDGPU: Select global saddr mode from SGPR pointerUse the 64-bit SGPR base with a 0 offset, since it&apos;s 1 fewerinstruction to materialize the 0 vs. the 64-bit copy.

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll</description>
        <pubDate>Tue, 10 Nov 2020 16:06:59 +0000</pubDate>
        <dc:creator>Matt Arsenault &lt;Matthew.Arsenault@amd.com&gt;</dc:creator>
    </item>
<item>
        <title>3fdf3b15 - AMDGPU: Update AMDHSA code object version handling</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll#3fdf3b15</link>
        <description>AMDGPU: Update AMDHSA code object version handlingDifferential Revision: https://reviews.llvm.org/D89076

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll</description>
        <pubDate>Wed, 14 Oct 2020 17:03:37 +0000</pubDate>
        <dc:creator>Konstantin Zhuravlyov &lt;kzhuravl_dev@outlook.com&gt;</dc:creator>
    </item>
<item>
        <title>acd0dd3a - [AMDGPU] Use lowercase for subtarget feature names in RUN lines</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll#acd0dd3a</link>
        <description>[AMDGPU] Use lowercase for subtarget feature names in RUN lines

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll</description>
        <pubDate>Tue, 13 Oct 2020 08:01:45 +0000</pubDate>
        <dc:creator>Jay Foad &lt;jay.foad@amd.com&gt;</dc:creator>
    </item>
<item>
        <title>b36a3e61 - [llvm-readobj] Update tests because of changes in llvm-readobj behavior</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll#b36a3e61</link>
        <description>[llvm-readobj] Update tests because of changes in llvm-readobj behaviorThis patch updates tests using llvm-readobj and llvm-readelf, becausesoon reading from stdin will be achievable only via a &apos;-&apos; as describedhere: https://bugs.llvm.org/show_bug.cgi?id=46400. Patch with changes tollvm-readobj behavior is here: https://reviews.llvm.org/D83704Differential Revision: https://reviews.llvm.org/D83912Reviewed by: jhenderson, MaskRay, grimar

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll</description>
        <pubDate>Mon, 20 Jul 2020 07:39:14 +0000</pubDate>
        <dc:creator>Elvina Yakubova &lt;elvina.yakubova@huawei.com&gt;</dc:creator>
    </item>
<item>
        <title>d3e170c4 - Revert &quot;[AMDGPU] Don&#8217;t marke the .note section as ALLOC&quot;</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll#d3e170c4</link>
        <description>Revert &quot;[AMDGPU] Don&#8217;t marke the .note section as ALLOC&quot;This reverts commit 977cd661cf019039dec7ffdd15bf0ac500828c87.It breaks OpenCL testing. OpenCL Runtime is using PT_LOAD informationto calculate memory for global variables. This commit should be relanded oncethe OpenCL runtime stops relying on PT_LOAD information for calculating globalvariable memory size.Differential Revision: https://reviews.llvm.org/D74995

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll</description>
        <pubDate>Fri, 21 Feb 2020 23:26:51 +0000</pubDate>
        <dc:creator>Mark Searles &lt;mark.searles@amd.com&gt;</dc:creator>
    </item>
<item>
        <title>977cd661 - [AMDGPU] Don&#8217;t marke the .note section as ALLOC</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll#977cd661</link>
        <description>[AMDGPU] Don&#8217;t marke the .note section as ALLOCMarking a section as ALLOC tells the ELF loader to load the section into memory.As we do not want to load the notes into VRAM, the flag should not be there.Differential Revision: https://reviews.llvm.org/D74600

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll</description>
        <pubDate>Thu, 13 Feb 2020 08:43:08 +0000</pubDate>
        <dc:creator>Sebastian Neubauer &lt;sebastian.neubauer@amd.com&gt;</dc:creator>
    </item>
<item>
        <title>e917b3b4 - [AMDGPU] gfx10 tests. NFC.</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll#e917b3b4</link>
        <description>[AMDGPU] gfx10 tests. NFC.llvm-svn: 363946

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll</description>
        <pubDate>Thu, 20 Jun 2019 16:29:40 +0000</pubDate>
        <dc:creator>Stanislav Mekhanoshin &lt;Stanislav.Mekhanoshin@amd.com&gt;</dc:creator>
    </item>
<item>
        <title>e29e30b1 - [llvm-readobj] Change -long-option to --long-option in tests. NFC</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll#e29e30b1</link>
        <description>[llvm-readobj] Change -long-option to --long-option in tests. NFCWe use both -long-option and --long-option in tests. Switch to --long-option for consistency.In the &quot;llvm-readelf&quot; mode, -long-option is discouraged as it conflicts with grouped short options and it is not accepted by GNU readelf.While updating the tests, change llvm-readobj -s to llvm-readobj -S to reduce confusion (&quot;s&quot; is --section-headers in llvm-readobj but --symbols in llvm-readelf).llvm-svn: 359649

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll</description>
        <pubDate>Wed, 01 May 2019 05:27:20 +0000</pubDate>
        <dc:creator>Fangrui Song &lt;maskray@google.com&gt;</dc:creator>
    </item>
<item>
        <title>a25e0524 - AMDGPU: Enable code object v3 for AMDHSA only</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll#a25e0524</link>
        <description>AMDGPU: Enable code object v3 for AMDHSA onlyDifferential Revision: https://reviews.llvm.org/D54186llvm-svn: 346923

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll</description>
        <pubDate>Thu, 15 Nov 2018 02:32:43 +0000</pubDate>
        <dc:creator>Konstantin Zhuravlyov &lt;kzhuravl_dev@outlook.com&gt;</dc:creator>
    </item>
<item>
        <title>2d22d24a - Revert r345542: AMDGPU: Enable code object v3 by default</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll#2d22d24a</link>
        <description>Revert r345542: AMDGPU: Enable code object v3 by defaultIt breaks mesa.llvm-svn: 345662

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll</description>
        <pubDate>Tue, 30 Oct 2018 22:02:40 +0000</pubDate>
        <dc:creator>Konstantin Zhuravlyov &lt;kzhuravl_dev@outlook.com&gt;</dc:creator>
    </item>
<item>
        <title>5cb95020 - AMDGPU: Enable code object v3 by default</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll#5cb95020</link>
        <description>AMDGPU: Enable code object v3 by defaultDifferential Revision: https://reviews.llvm.org/D53525llvm-svn: 345542

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll</description>
        <pubDate>Mon, 29 Oct 2018 21:07:27 +0000</pubDate>
        <dc:creator>Konstantin Zhuravlyov &lt;kzhuravl_dev@outlook.com&gt;</dc:creator>
    </item>
<item>
        <title>23e4df6a - AMDGPU: Detect kernarg segment pointer</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll#23e4df6a</link>
        <description>AMDGPU: Detect kernarg segment pointerThis is necessary to pass the kernarg segment pointerto callee functions. Also don&apos;t unconditionally enablefor kernels.llvm-svn: 307978

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll</description>
        <pubDate>Fri, 14 Jul 2017 00:11:13 +0000</pubDate>
        <dc:creator>Matt Arsenault &lt;Matthew.Arsenault@amd.com&gt;</dc:creator>
    </item>
<item>
        <title>5d910194 - AMDGPU: Set call_convention bit in kernel_code_t</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll#5d910194</link>
        <description>AMDGPU: Set call_convention bit in kernel_code_tAccording to the documentation this is supposed to be -1if indirect calls are not supported.llvm-svn: 293081

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll</description>
        <pubDate>Wed, 25 Jan 2017 20:21:57 +0000</pubDate>
        <dc:creator>Matt Arsenault &lt;Matthew.Arsenault@amd.com&gt;</dc:creator>
    </item>
<item>
        <title>67a6d540 - [AMDGPU] Do not emit .AMDGPU.config section for amdhsa</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll#67a6d540</link>
        <description>[AMDGPU] Do not emit .AMDGPU.config section for amdhsaDifferential Revision: https://reviews.llvm.org/D27732llvm-svn: 291245

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll</description>
        <pubDate>Fri, 06 Jan 2017 17:02:10 +0000</pubDate>
        <dc:creator>Konstantin Zhuravlyov &lt;kzhuravl_dev@outlook.com&gt;</dc:creator>
    </item>
<item>
        <title>98a3ac71 - [AMDGPU] Mark .note section SHF_ALLOC so lld creates a segment for it</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll#98a3ac71</link>
        <description>[AMDGPU] Mark .note section SHF_ALLOC so lld creates a segment for itDifferential Revision: https://reviews.llvm.org/D25694llvm-svn: 284435

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll</description>
        <pubDate>Mon, 17 Oct 2016 22:40:15 +0000</pubDate>
        <dc:creator>Konstantin Zhuravlyov &lt;kzhuravl_dev@outlook.com&gt;</dc:creator>
    </item>
<item>
        <title>418beb76 - AMDGPU/SI: Add support for R_AMDGPU_GOTPCREL</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll#418beb76</link>
        <description>AMDGPU/SI: Add support for R_AMDGPU_GOTPCRELReviewers: rafael, ruiu, tony-tye, arsenm, kzhuravlSubscribers: arsenm, llvm-commits, kzhuravlDifferential Revision: http://reviews.llvm.org/D21484llvm-svn: 275268

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll</description>
        <pubDate>Wed, 13 Jul 2016 14:23:33 +0000</pubDate>
        <dc:creator>Tom Stellard &lt;thomas.stellard@amd.com&gt;</dc:creator>
    </item>
<item>
        <title>1f7732ab - AMDGPU/SI: Add amdgpu_kernel calling convention. Part 1.</title>
        <link>http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll#1f7732ab</link>
        <description>AMDGPU/SI: Add amdgpu_kernel calling convention. Part 1.Summary:This will be used for AMDGPU_HSA_KERNEL symbol type in output ELF.Also, in the future unused non-kernels may be optimized.For now, also accept SPIR_KERNEL for HCC frontend.Also, add bitcode compatibility tests for missing calling conventionsexcept AVR_BUILTIN which doesn&apos;t have parse code.Reviewers: tstellarAMD, arsenmSubscribers: arsenm, joker.eph, llvm-commitsllvm-svn: 268717

            List of files:
            /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hsa.ll</description>
        <pubDate>Fri, 06 May 2016 09:07:29 +0000</pubDate>
        <dc:creator>Nikolay Haustov &lt;Nikolay.Haustov@amd.com&gt;</dc:creator>
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