en Copyright 2015 Java http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hazard-kill.mir#3bffb1cd [AMDGPU] Use single cache policy operandReplace individual operands GLC, SLC, and DLC with a single cache_policybitmask operand. This will reduce the number of operands in MIR and I hopethe amount of code. These operands are mostly 0 anyway.Additional advantage that parser will accept these flags in any order unlikenow.Differential Revision: https://reviews.llvm.org/D96469 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hazard-kill.mir Tue, 09 Feb 2021 00:36:10 +0000 Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hazard-kill.mir#4b449631 AMDGPU: Start adding MODE register uses to instructionsThis is the groundwork required to implement strictfp. For now, thisshould be NFC for regular instructoins (many instructions just gain anextra use of a reserved register). Regalloc won't rematerializeinstructions with reads of physical registers, but we were sufferingfrom that anyway with the exec reads.Should add it for all the related FP uses (possibly with someextras). I did not add it to either the gpr index mode instructions(or every single VALU instruction) since it's a ridiculous featurealready modeled as an arbitrary side effect.Also work towards marking instructions with FP exceptions. Thisdoesn't actually set the bit yet since this would start to changecodegen. It seems nofpexcept is currently not implied from the regularIR FP operations. Add it to some MIR tests where I think it mightmatter. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hazard-kill.mir Wed, 27 May 2020 17:25:37 +0000 Matt Arsenault <Matthew.Arsenault@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hazard-kill.mir#a6322941 [AMDGPU] gfx1010 VMEM and SMEM implementationDifferential Revision: https://reviews.llvm.org/D61330llvm-svn: 359621 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hazard-kill.mir Tue, 30 Apr 2019 22:08:23 +0000 Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hazard-kill.mir#20ea21c6 [AMDGPU] Add support for immediate operand for S_ENDPGMSummary:Add support for immediate operand in S_ENDPGMChange-Id: I0c56a076a10980f719fb2a8f16407e9c301013f6Reviewers: alexshapSubscribers: qcolombet, arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, eraman, arphaman, Petar.Avramovic, llvm-commitsTags: #llvmDifferential Revision: https://reviews.llvm.org/D59213llvm-svn: 355902 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hazard-kill.mir Tue, 12 Mar 2019 09:52:58 +0000 David Stuttard <david.stuttard@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hazard-kill.mir#81eec58a [AMDGPU] Omit KILL instructions from hazard recognizerSummary:In some cases the KILL was causing a hazard to be introduced as these werescheduled into hazard slots, but don't result in an instruction.KILL shouldn't be considered for hazard recognition.Change-Id: Ib6d2a2160f8c94cd0ce611ab198c7e4f46aeffcfSubscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, llvm-commitsTags: #llvmDifferential Revision: https://reviews.llvm.org/D58898llvm-svn: 355384 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/hazard-kill.mir Tue, 05 Mar 2019 10:25:16 +0000 David Stuttard <david.stuttard@amd.com>