en Copyright 2015 Java http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/fceil64.ll#62d8b8a2 Fix 64-bit copy to SCCFix 64-bit copy to SCC by restricting the pattern resultingin such a copy to subtargets supporting 64-bit scalar compare,and mapping the copy to S_CMP_LG_U64.Before introducing the S_CSELECT pattern with explicit SCC(0045786f146e78afee49eee053dc29ebc842fee1), there was no needfor handling 64-bit copy to SCC ($scc = COPY sreg_64).The proposed handling to read only the low bits was howeverbased on a false premise that it is only one bit that matters,while in fact the copy source might be a vector of booleans andall bits need to be considered.The practical problem of mapping the 64-bit copy to SCC is thatthe natural instruction to use (S_CMP_LG_U64) is not availableon old hardware. Fix it by restricting the problematic patternto subtargets supporting the instruction (hasScalarCompareEq64).Differential Revision: https://reviews.llvm.org/D85207 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/fceil64.ll Thu, 30 Jul 2020 11:56:06 +0000 Piotr Sobczak <Piotr.Sobczak@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/fceil64.ll#0045786f [AMDGPU] Select s_cselectSummary:Add patterns to select s_cselect in the isel.Handle more cases of implicit SCC accesses in si-fix-sgpr-copiesto allow new patterns to work.Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, asbirlea, kerbowa, llvm-commitsTags: #llvmRe-commit D81925 with a bugfix D82370.Differential Revision: https://reviews.llvm.org/D81925Differential Revision: https://reviews.llvm.org/D82370 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/fceil64.ll Wed, 04 Mar 2020 14:13:08 +0000 Piotr Sobczak <Piotr.Sobczak@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/fceil64.ll#6d9565d6 Revert "[AMDGPU] Select s_cselect"This caused some failures detected by the buildbot withexpensive checks enabled.This reverts commit 4067de569f119a81419fbf2e79d5f3307dfdda5b. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/fceil64.ll Fri, 19 Jun 2020 14:39:55 +0000 Piotr Sobczak <Piotr.Sobczak@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/fceil64.ll#4067de56 [AMDGPU] Select s_cselectSummary:Add patterns to select s_cselect in the isel.Handle more cases of implicit SCC accesses in si-fix-sgpr-copiesto allow new patterns to work.Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, asbirlea, kerbowa, llvm-commitsTags: #llvmDifferential Revision: https://reviews.llvm.org/D81925 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/fceil64.ll Wed, 04 Mar 2020 14:13:08 +0000 Piotr Sobczak <Piotr.Sobczak@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/fceil64.ll#04f7a4d2 [AMDGPU] Add and update scalar instructionsThis patch adds support for S_ANDN2, S_ORN2 32-bit and 64-bit instructions and adds splits to move them to the vector unit (for which there is no equivalent instruction). It modifies the way that the more complex scalar instructions are lowered to vector instructions by first breaking them down to sequences of simpler scalar instructions which are then lowered through the existing code paths. The pattern for S_XNOR has also been updated to apply inversion to one input rather than the output of the XOR as the result is equivalent and may allow leaving the NOT instruction on the scalar unit.A new tests for NAND, NOR, ANDN2 and ORN2 have been added, and existing tests now hit the new instructions (and have been modified accordingly).Differential: https://reviews.llvm.org/D54714llvm-svn: 347877 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/fceil64.ll Thu, 29 Nov 2018 16:05:38 +0000 Graham Sellers <graham.sellers@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/fceil64.ll#9fa9c936 [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm testsSee https://reviews.llvm.org/D47106 for details.Reviewed By: probinsonDifferential Revision: https://reviews.llvm.org/D47171This commit drops that patch's changes to: llvm/test/CodeGen/NVPTX/f16x2-instructions.ll llvm/test/CodeGen/NVPTX/param-load-store.llFor some reason, the dos line endings there prevent me from commitingvia the monorepo. A follow-up commit (not via the monorepo) willfinish the patch.llvm-svn: 336843 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/fceil64.ll Wed, 11 Jul 2018 20:25:49 +0000 Joel E. Denny <jdenny.ornl@gmail.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/fceil64.ll#3dbeefa9 AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernelCurrently the default C calling convention functions are treatedthe same as compute kernels. Make this explicit so the defaultcalling convention can be changed to a non-kernel.Converted with perl -pi -e 's/define void/define amdgpu_kernel void/'on the relevant test directories (and undoing in one place that actuallywanted a non-kernel).llvm-svn: 298444 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/fceil64.ll Tue, 21 Mar 2017 21:39:51 +0000 Matt Arsenault <Matthew.Arsenault@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/fceil64.ll#bbb47da8 AMDGPU: Support commuting with immediate in src0llvm-svn: 280970 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/fceil64.ll Thu, 08 Sep 2016 17:19:29 +0000 Matt Arsenault <Matthew.Arsenault@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/fceil64.ll#0d23ebe8 AMDGPU/SI: Implement a custom MachineSchedStrategySummary:GCNSchedStrategy re-uses most of GenericScheduler, it's just usesa different method to compute the excess and critical registerpressure limits.It's not enabled by default, to enable it you need to pass -misched=gcnto llc.Shader DB stats:32464 shaders in 17874 testsTotals:SGPRS: 1542846 -> 1643125 (6.50 %)VGPRS: 1005595 -> 904653 (-10.04 %)Spilled SGPRs: 29929 -> 27745 (-7.30 %)Spilled VGPRs: 334 -> 352 (5.39 %)Scratch VGPRs: 1612 -> 1624 (0.74 %) dwords per threadCode Size: 36688188 -> 37034900 (0.95 %) bytesLDS: 1913 -> 1913 (0.00 %) blocksMax Waves: 254101 -> 265125 (4.34 %)Wait states: 0 -> 0 (0.00 %)Totals from affected shaders:SGPRS: 1338220 -> 1438499 (7.49 %)VGPRS: 886221 -> 785279 (-11.39 %)Spilled SGPRs: 29869 -> 27685 (-7.31 %)Spilled VGPRs: 334 -> 352 (5.39 %)Scratch VGPRs: 1612 -> 1624 (0.74 %) dwords per threadCode Size: 34315716 -> 34662428 (1.01 %) bytesLDS: 1551 -> 1551 (0.00 %) blocksMax Waves: 188127 -> 199151 (5.86 %)Wait states: 0 -> 0 (0.00 %)Reviewers: arsenm, mareko, nhaehnle, MatzeB, atrickSubscribers: arsenm, kzhuravl, llvm-commitsDifferential Revision: https://reviews.llvm.org/D23688llvm-svn: 279995 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/fceil64.ll Mon, 29 Aug 2016 19:42:52 +0000 Tom Stellard <thomas.stellard@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/fceil64.ll#c2ff0eb6 AMDGPU/SI: Improve SILoadStoreOptimizer and run it before the schedulerSummary:The SILoadStoreOptimizer can now look ahead more then one instruction whenlooking for instructions to merge, which greatly improves the number ofloads/stores that we are able to merge.Moving the pass before scheduling avoids increasing register pressure afterthe scheduler, so that the scheduler's register pressure estimates will bemore accurate. It also gives more consistent results, since it is no longeraffected by minor scheduling changes.Reviewers: arsenmSubscribers: arsenm, kzhuravl, llvm-commitsDifferential Revision: https://reviews.llvm.org/D23814llvm-svn: 279991 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/fceil64.ll Mon, 29 Aug 2016 19:15:22 +0000 Tom Stellard <thomas.stellard@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/fceil64.ll#13548776 [AMDGPU][llvm-mc] v_cndmask_b32: src2 is mandatory; do not enforce VOP2 when src2 == VCC.Another step for unification llvm assembler/disassembler with sp3.Besides, CodeGen output is a bit improved, thus changes in CodeGen tests.Assembler/Disassembler tests updated/added.Differential Revision: http://reviews.llvm.org/D20796llvm-svn: 271900 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/fceil64.ll Mon, 06 Jun 2016 15:23:43 +0000 Artem Tamazov <artem.tamazov@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/fceil64.ll#71369b3a AMDGPU/SI: Enable load-store-opt by default.Summary: Enable load-store-opt by default, and update LIT tests.Reviewers: arsenmDifferential Revision: http://reviews.llvm.org/D20694llvm-svn: 270894 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/fceil64.ll Thu, 26 May 2016 19:35:29 +0000 Changpeng Fang <changpeng.fang@gmail.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/fceil64.ll#b6be2027 AMDGPU: Use s_addk_i32 / s_mulk_i32llvm-svn: 266506 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/fceil64.ll Sat, 16 Apr 2016 01:46:49 +0000 Matt Arsenault <Matthew.Arsenault@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/fceil64.ll#7900334d AMDGPU: Fold bitcasts of scalar constants to vectorsThis cleans up some messes since the individual scalar componentscan be CSEed.llvm-svn: 266376 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/fceil64.ll Thu, 14 Apr 2016 21:58:07 +0000 Matt Arsenault <Matthew.Arsenault@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/fceil64.ll#1d5e6d4b AMDGPU/SI: Improve MachineSchedModel definitionThis patch contains a few improvements to the model, including:- Using a single resource with a defined buffers size for each memory unit.- Setting the IssueWidth correctly.- Fixing latency values for memory instructions.shader-db stats:16429 shaders in 3231 testsTotals:SGPRS: 318232 -> 312328 (-1.86 %)VGPRS: 208996 -> 209346 (0.17 %)Code Size: 7147044 -> 7166440 (0.27 %) bytesLDS: 83 -> 83 (0.00 %) blocksScratch: 1862656 -> 1459200 (-21.66 %) bytes per waveMax Waves: 49182 -> 49243 (0.12 %)Wait states: 0 -> 0 (0.00 %)ADifferential Revision: http://reviews.llvm.org/D18453llvm-svn: 264877 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/fceil64.ll Wed, 30 Mar 2016 16:35:13 +0000 Tom Stellard <thomas.stellard@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/fceil64.ll#61dc235f DAGCombiner: Combine extract_vector_elt from build_vectorThis basic combine was surprisingly missing.AMDGPU legalizes many operations in terms of 32-bit vector components,so not doing this results in many extra copies and subregister extractsthat need to be cleaned up later.InstCombine already does this for the hasOneUse case. The target hookis to fix a handful of tests which break (e.g. ARM/vmov.ll) which turnfrom a vector materialize repeated immediate instruction to a constantvector load with more scalar copies from it.llvm-svn: 250129 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/fceil64.ll Mon, 12 Oct 2015 23:59:50 +0000 Matt Arsenault <Matthew.Arsenault@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/fceil64.ll#45bb48ea R600 -> AMDGPU renamellvm-svn: 239657 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/fceil64.ll Sat, 13 Jun 2015 03:28:10 +0000 Tom Stellard <thomas.stellard@amd.com>