Changes in cf-loop-on-constant.ll

2e29b013 - [AMDGPU] Lowering VGPR to SGPR copies to v_readfirstlane_b32 if profitable.

Tue, 21 Jun 2022 08:57:58 +0000

[AMDGPU] Lowering VGPR to SGPR copies to v_readfirstlane_b32 if profitable.Since the divergence-driven instruction selection has been enabled for AMDGPU, all the uniform instructions are expected to be selected to SALU form, except those not having one. VGPR to SGPR copies appear in MIR to connect values producers and consumers. This change implements an algorithm that evolves a reasonable tradeoff between the profit achieved from keeping the uniform instructions in SALU form and overhead introduced by the data transfer between the VGPRs and SGPRs.Reviewed By: rampitecDifferential Revision: https://reviews.llvm.org/D128252 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll

18f93512 - [AMDGPU] Do not generate ELF symbols for the local branch target labels

Fri, 19 Nov 2021 20:23:38 +0000

[AMDGPU] Do not generate ELF symbols for the local branch target labelsThe compiler was generating symbols in the final code object for localbranch target labels. This bloats the code object, slows down the loader,and is only used to simplify disassembly.Use '--symbolize-operands' with llvm-objdump to improve readability of thebranch target operands in disassembly.Fixes: SWDEV-312223Reviewed By: scott.linderDifferential Revision: https://reviews.llvm.org/D114273 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll

bf147c46 - [LSR] Fix for pre-indexed generated constant offset

Thu, 15 Apr 2021 15:44:42 +0000

[LSR] Fix for pre-indexed generated constant offsetThis patch changed the isLegalUse check to ensure thatLSRInstance::GenerateConstantOffsetsImpl generates anoffset that results in a legal addressing mode andformula. The check is changed to look similar to theassert check used for illegal formulas.Differential Revision: https://reviews.llvm.org/D100383Change-Id: Iffb9e32d59df96b8f072c00f6c339108159a009a List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll

6fec0a34 - [AMDGPU] Fix typo in regular expression checks. NFC.

Tue, 06 Apr 2021 11:29:48 +0000

[AMDGPU] Fix typo in regular expression checks. NFC. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll

72e87549 - [AMDGPU] Disable 'Skip Uniform Regions' optimization by default for AMDGPU.

Mon, 06 Apr 2020 13:05:58 +0000

[AMDGPU] Disable 'Skip Uniform Regions' optimization by default for AMDGPU.Reviewers: sameerds, dstuttardDifferential Revision: https://reviews.llvm.org/D77228 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll

51dc0283 - Revert e1730cfeb3588f20dcf4a96b181ad52761666e52

Mon, 06 Apr 2020 09:56:11 +0000

Revert e1730cfeb3588f20dcf4a96b181ad52761666e52 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll

e1730cfe - [AMDGPU] Disable 'Skip Uniform Regions' optimization by default for AMDGPU.

Mon, 06 Apr 2020 09:10:37 +0000

90083d30 - AMDGPU: Try a lot harder to emit scalar loads

Thu, 07 Jun 2018 09:54:49 +0000

AMDGPU: Try a lot harder to emit scalar loadsThis has two main components. First, widenwiden short constant loads in DAG when they havethe correct alignment. This is already done a bit inAMDGPUCodeGenPrepare, since that has access toDivergenceAnalysis. This can't help kernarg loadscreated in the DAG. Start to use DAG divergence analysisto help this case.The second part is to avoid kernel argument loweringbreaking the alignment of short vector elements becausecalling convention lowering wants to split everythinginto legal register types.When loading a split type, load the nearest 4-byte alignedsegment and shift to get the desired bits. This extraload of the earlier argument piece ends up merging,and the bit extract hopefully folds out.There are a number of improvements and regressions withthis, but I think as-is this is a better compromise betweenseveral of the worst parts of SelectionDAG.Particularly when i16 is legal, this produces worse codefor i8 and i16 element vector kernel arguments. This ispartially due to the very weak load merging the DAG does.It only looks for fairly specific combines between pairsof loads which no longer appear. In particular thiscauses v4i16 loads to be split into 2 components whenpreviously the two halves were merged.Worse, because of the newly introduced shifts, thereis a lot more unnecessary vector packing and unpacking codeemitted. At least some of this is due to reportingfalse for isTypeDesirableForOp for i16 as a workaround forthe lack of divergence information in the DAG. The caseswhere this happens it doesn't actually matter, but therelevant code in SimplifyDemandedBits doens't have the contextto know to ignore this.The use of the scalar cache is probably more importantthan the mess of mostly scalar instructions doing this packingand unpacking. Future work can fix this, possibly by making betteruse of the new DAG divergence information for controlling promotiondecisions, or adding another version of shift + trunc + shiftcombines that doesn't only know about the used types.llvm-svn: 334180 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll

391bcf88 - AMDGPU/SI: Handle infinite loop for the structurizer to work with CFG with infinite loops.

Thu, 17 May 2018 16:45:01 +0000

AMDGPU/SI: Handle infinite loop for the structurizer to work with CFG with infinite loops.Summary: The current StructurizeCFG pass only works for CFG with one exit. AMDGPUUnifyDivergentExitNodes combines multiple "return" blocks and/or "unreachable" blocksto one exit block for the Structurizer to work. However, infinite loop is another kind of special "exit", and if we don't handle it, the case of multiple exits will prevent the structurizer from working.In this work, for each infinite loop, we add a dummy edge to the "return" block, and thus the AMDGPUUnifyDivergentExitNodes pass will work with infinite loops.This will make CFG with infinite loops be structurized.Reviewer: nhaehnleDifferential Revision: https://reviews.llvm.org/D46340llvm-svn: 332625 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll

6eaad1e5 - [AMDGPU] Fixed incorrect uniform branch condition

Tue, 09 Jan 2018 21:34:43 +0000

[AMDGPU] Fixed incorrect uniform branch conditionSummary:I had a case where multiple nested uniform ifs resulted in code that didv_cmp comparisons, combining the results with s_and_b64, s_or_b64 ands_xor_b64 and using the resulting mask in s_cbranch_vccnz, without firstensuring that bits for inactive lanes were clear.There was already code for inserting an "s_and_b64 vcc, exec, vcc" toclear bits for inactive lanes in the case that the branch is instructionselected as s_cbranch_scc1 and is then changed to s_cbranch_vccnz inSIFixSGPRCopies. I have added the same code into SILowerControlFlow forthe case that the branch is instruction selected as s_cbranch_vccnz.This de-optimizes the code in some cases where the s_and is not needed,because vcc is the result of a v_cmp, or multiple v_cmp instructionscombined by s_and/s_or. We should add a pass to re-optimize those cases.Reviewers: arsenm, kzhuravlSubscribers: wdng, yaxunl, t-tye, llvm-commits, dstuttard, timcorringham, nhaehnleDifferential Revision: https://reviews.llvm.org/D41292llvm-svn: 322119 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll

25528d6d - [CodeGen] Unify MBB reference format in both MIR and debug output

Mon, 04 Dec 2017 17:18:51 +0000

[CodeGen] Unify MBB reference format in both MIR and debug outputAs part of the unification of the debug format and the MIR format, printMBB references as '%bb.5'.The MIR printer prints the IR name of a MBB only for block definitions.* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g'* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g'* find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g'* grep -nr 'BB#' and fixDifferential Revision: https://reviews.llvm.org/D40422llvm-svn: 319665 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll

3dbeefa9 - AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel

Tue, 21 Mar 2017 21:39:51 +0000

AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernelCurrently the default C calling convention functions are treatedthe same as compute kernels. Make this explicit so the defaultcalling convention can be changed to a non-kernel.Converted with perl -pi -e 's/define void/define amdgpu_kernel void/'on the relevant test directories (and undoing in one place that actuallywanted a non-kernel).llvm-svn: 298444 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll

7fbec9bd - Codegen: Make chains from trellis-shaped CFGs

Wed, 15 Feb 2017 19:49:14 +0000

Codegen: Make chains from trellis-shaped CFGsLay out trellis-shaped CFGs optimally.A trellis of the shape below: A B |\ /| | \ / | | X | | / \ | |/ \| C Dwould be laid out A; B->C ; D by the current layout algorithm. Now we identifytrellises and lay them out either A->C; B->D or A->D; B->C. This scales with anincreasing number of predecessors. A trellis is a a group of 2 or morepredecessor blocks that all have the same successors.because of this we can tail duplicate to extend existing trellises.As an example consider the following CFG: B D F H / \ / \ / \ / \ A---C---E---G---RetWhere A,C,E,G are all small (Currently 2 instructions).The CFG preserving layout is then A,B,C,D,E,F,G,H,Ret.The current code will copy C into B, E into D and G into F and yield the layoutA,C,B(C),E,D(E),F(G),G,H,retdefine void @straight_test(i32 %tag) {entry: br label %test1test1: ; A %tagbit1 = and i32 %tag, 1 %tagbit1eq0 = icmp eq i32 %tagbit1, 0 br i1 %tagbit1eq0, label %test2, label %optional1optional1: ; B call void @a() br label %test2test2: ; C %tagbit2 = and i32 %tag, 2 %tagbit2eq0 = icmp eq i32 %tagbit2, 0 br i1 %tagbit2eq0, label %test3, label %optional2optional2: ; D call void @b() br label %test3test3: ; E %tagbit3 = and i32 %tag, 4 %tagbit3eq0 = icmp eq i32 %tagbit3, 0 br i1 %tagbit3eq0, label %test4, label %optional3optional3: ; F call void @c() br label %test4test4: ; G %tagbit4 = and i32 %tag, 8 %tagbit4eq0 = icmp eq i32 %tagbit4, 0 br i1 %tagbit4eq0, label %exit, label %optional4optional4: ; H call void @d() br label %exitexit: ret void}here is the layout after D27742:straight_test: # @straight_test; ... Prologue elided; BB#0: # %entry ; A (merged with test1); ... More prologue elided mr 30, 3 andi. 3, 30, 1 bc 12, 1, .LBB0_2; BB#1: # %test2 ; C rlwinm. 3, 30, 0, 30, 30 beq 0, .LBB0_3 b .LBB0_4.LBB0_2: # %optional1 ; B (copy of C) bl a nop rlwinm. 3, 30, 0, 30, 30 bne 0, .LBB0_4.LBB0_3: # %test3 ; E rlwinm. 3, 30, 0, 29, 29 beq 0, .LBB0_5 b .LBB0_6.LBB0_4: # %optional2 ; D (copy of E) bl b nop rlwinm. 3, 30, 0, 29, 29 bne 0, .LBB0_6.LBB0_5: # %test4 ; G rlwinm. 3, 30, 0, 28, 28 beq 0, .LBB0_8 b .LBB0_7.LBB0_6: # %optional3 ; F (copy of G) bl c nop rlwinm. 3, 30, 0, 28, 28 beq 0, .LBB0_8.LBB0_7: # %optional4 ; H bl d nop.LBB0_8: # %exit ; Ret ld 30, 96(1) # 8-byte Folded Reload addi 1, 1, 112 ld 0, 16(1) mtlr 0 blrThe tail-duplication has produced some benefit, but it has also produced atrellis which is not laid out optimally. With this patch, we improve the layoutsof such trellises, and decrease the cost calculation for tail-duplicationaccordingly.This patch produces the layout A,C,E,G,B,D,F,H,Ret. This layout does haveback edges, which is a negative, but it has a bigger compensatingpositive, which is that it handles the case where there are long stringsof skipped blocks much better than the original layout. Both layoutshandle runs of executed blocks equally well. Branch prediction alsoimproves if there is any correlation between subsequent optional blocks.Here is the resulting concrete layout:straight_test: # @straight_test; BB#0: # %entry ; A (merged with test1) mr 30, 3 andi. 3, 30, 1 bc 12, 1, .LBB0_4; BB#1: # %test2 ; C rlwinm. 3, 30, 0, 30, 30 bne 0, .LBB0_5.LBB0_2: # %test3 ; E rlwinm. 3, 30, 0, 29, 29 bne 0, .LBB0_6.LBB0_3: # %test4 ; G rlwinm. 3, 30, 0, 28, 28 bne 0, .LBB0_7 b .LBB0_8.LBB0_4: # %optional1 ; B (Copy of C) bl a nop rlwinm. 3, 30, 0, 30, 30 beq 0, .LBB0_2.LBB0_5: # %optional2 ; D (Copy of E) bl b nop rlwinm. 3, 30, 0, 29, 29 beq 0, .LBB0_3.LBB0_6: # %optional3 ; F (Copy of G) bl c nop rlwinm. 3, 30, 0, 28, 28 beq 0, .LBB0_8.LBB0_7: # %optional4 ; H bl d nop.LBB0_8: # %exitDifferential Revision: https://reviews.llvm.org/D28522llvm-svn: 295223 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll

0bc68811 - AMDGPU/SI: Avoid moving PHIs to VALU when phi values are defined in scalar branches

Tue, 29 Nov 2016 00:46:46 +0000

AMDGPU/SI: Avoid moving PHIs to VALU when phi values are defined in scalar branchesReviewers: arsenmSubscribers: arsenm, llvm-commits, kzhuravlDifferential Revision: https://reviews.llvm.org/D23417llvm-svn: 288095 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll

f530e8b3 - AMDGPU: Remove unnecessary and on conditional branch

Mon, 07 Nov 2016 19:09:33 +0000

AMDGPU: Remove unnecessary and on conditional branchThe comment explaining why this was necessary is incorrectin its description of v_cmp's behavior for inactive workitems.llvm-svn: 286134 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll

5d8eb25e - AMDGPU: Use unsigned compare for eq/ne

Fri, 30 Sep 2016 01:50:20 +0000

AMDGPU: Use unsigned compare for eq/neFor some reason there are both of these available, exceptfor scalar 64-bit compares which only has u64. I'm not surewhy there are both (I'm guessing it's for the one bit inputs wedon't use), but for consistency always using theunsigned one.llvm-svn: 282832 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll

0534f4aa - AMDGPU: Un-xfail and add tests

Fri, 24 Jun 2016 06:58:01 +0000

AMDGPU: Un-xfail and add testsUn XFAIL a few tests plus a few more I had lying aroundin my tree, which seem to all work now but I don't see teststhat quite test the same things.llvm-svn: 273655 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll