en Copyright 2015 Java http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/calling-conventions.ll#2214bc81 AMDGPU: Allow i16 shader argumentsNot allowing this just creates unnecessary complications when writingsimple tests. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/calling-conventions.ll Sun, 26 Jan 2020 23:24:24 +0000 Matt Arsenault <Matthew.Arsenault@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/calling-conventions.ll#a85af76c AMDGPU: Don't assert on v4f16 arguments to shader calling conventionsllvm-svn: 367018 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/calling-conventions.ll Thu, 25 Jul 2019 13:55:07 +0000 Matt Arsenault <Matthew.Arsenault@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/calling-conventions.ll#82099457 [DAG] Refactor DAGCombiner::ReassociateOpsSummary:Extract the logic for doing reassociationsfrom DAGCombiner::reassociateOps into a helperfunction DAGCombiner::reassociateOpsCommutative,and use that helper to trigger reassociationon the original operand order, or the commutedoperand order.Codegen is not identical since the operand order willbe different when doing the reassociations for thecommuted case. That causes some unfortunate churn insome test cases. Apart from that this should be NFC.Reviewers: spatel, craig.topper, tstellarReviewed By: spatelSubscribers: dmgreen, dschuff, jvesely, nhaehnle, javed.absar, sbc100, jgravelle-google, hiraditya, aheejin, llvm-commitsTags: #llvmDifferential Revision: https://reviews.llvm.org/D61199llvm-svn: 359476 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/calling-conventions.ll Mon, 29 Apr 2019 17:50:10 +0000 Bjorn Pettersson <bjorn.a.pettersson@ericsson.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/calling-conventions.ll#f97b29be [DAGCombiner] Combine OR as ADD when no common bits are setSummary:The DAGCombiner is rewriting (canonicalizing) an ISD::ADDwith no common bits set in the operands as an ISD::OR node.This could sometimes result in "missing out" on somecombines that normally are performed for ADD. To be morespecific this could happen if we already have rewritten anADD into OR, and later (after legalizations or combines)we expose patterns that could have been optimized if wehad seen the OR as an ADD (e.g. reassociations based on ADD).To make the DAG combiner less sensitive to if ADD or OR isused for these "no common bits set" ADD/OR operations wenow apply most of the ADD combines also to an OR operation,when value tracking indicates that the operands have nocommon bits set.Reviewers: spatel, RKSimon, craig.topper, kparzyszReviewed By: spatelSubscribers: arsenm, rampitec, lebedev.ri, jvesely, nhaehnle, hiraditya, javed.absar, llvm-commitsTags: #llvmDifferential Revision: https://reviews.llvm.org/D59758llvm-svn: 358965 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/calling-conventions.ll Tue, 23 Apr 2019 10:01:08 +0000 Bjorn Pettersson <bjorn.a.pettersson@ericsson.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/calling-conventions.ll#fe59e140 [DAGCombine] Prune unnused nodes.Summary:Nodes that have no uses are eventually pruned when they are selectedfrom the worklist. Record nodes newly added to the worklist or DAG andperform pruning after every combine attempt.Reviewers: efriedma, RKSimon, craig.topper, spatel, jyknightReviewed By: jyknightSubscribers: jdoerfert, jyknight, nemanjai, jvesely, nhaehnle, javed.absar, hiraditya, jsji, llvm-commitsTags: #llvmDifferential Revision: https://reviews.llvm.org/D58070llvm-svn: 357283 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/calling-conventions.ll Fri, 29 Mar 2019 17:35:56 +0000 Nirav Dave <niravd@google.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/calling-conventions.ll#e30aa6a1 [AMDGPU] Prepare for introduction of v3 and v5 MVTsAMDGPU would like to have MVTs for v3i32, v3f32, v5i32, v5f32. Thiscommit does not add them, but makes preparatory changes:* Fixed assumptions of power-of-2 vector type in kernel arg handling, and added v5 kernel arg tests and v3/v5 shader arg tests.* Added v5 tests for cost analysis.* Added vec3/vec5 arg test cases.Some of this patch is from Matt Arsenault, also of AMD.Differential Revision: https://reviews.llvm.org/D58928Change-Id: I7279d6b4841464d2080eb255ef3c589e268eabcdllvm-svn: 356342 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/calling-conventions.ll Sun, 17 Mar 2019 21:04:16 +0000 Tim Renouf <tpr.llvm@botech.co.uk> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/calling-conventions.ll#55ab9213 AMDGPU: Partially fix handling of packed amdgpu_ps argumentsFixes annoying limitations when writing tests.Also remove more leftover code for manually scalarizing argumentsand return values.llvm-svn: 338618 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/calling-conventions.ll Wed, 01 Aug 2018 19:57:34 +0000 Matt Arsenault <Matthew.Arsenault@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/calling-conventions.ll#ef1ae8ff [AMDGPU] calling conventions for AMDPAL OS typeSummary:This commit adds comments on how the AMDPAL OS type overloads theexisting AMDGPU_ calling conventions used by Mesa, and adds a couple ofnew ones.Reviewers: arsenm, nhaehnle, dstuttardSubscribers: mehdi_amini, kzhuravl, wdng, yaxunl, t-tye, llvm-commitsDifferential Revision: https://reviews.llvm.org/D37752llvm-svn: 314502 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/calling-conventions.ll Fri, 29 Sep 2017 09:51:22 +0000 Tim Renouf <tim.renouf@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/calling-conventions.ll#537bd3b9 AMDGPU: Allow coldcc callsllvm-svn: 312936 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/calling-conventions.ll Mon, 11 Sep 2017 18:54:20 +0000 Matt Arsenault <Matthew.Arsenault@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/calling-conventions.ll#efa9f4b2 AMDGPU: Refactor SIMachineFunctionInfo slightlyPrepare for handling non-entry functions.llvm-svn: 299999 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/calling-conventions.ll Tue, 11 Apr 2017 22:29:28 +0000 Matt Arsenault <Matthew.Arsenault@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/calling-conventions.ll#e2d1d3a9 AMDGPU: Add f16 to shader calling conventionsMostly useful for writing tests for f16 features.llvm-svn: 296370 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/calling-conventions.ll Mon, 27 Feb 2017 19:24:47 +0000 Matt Arsenault <Matthew.Arsenault@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/calling-conventions.ll#0fbf899c AMDGPU/SI: Remove calling convention assertion from LowerFormalArguments()Summary:We currently ignore the calling convention, so there is no real reason toassert on the calling convention of functions.Reviewers: arsenmSubscribers: arsenm, llvm-commitsDifferential Revision: http://reviews.llvm.org/D13367llvm-svn: 249468 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/calling-conventions.ll Tue, 06 Oct 2015 21:16:34 +0000 Tom Stellard <thomas.stellard@amd.com>