Changes in llvm.amdgcn.struct.tbuffer.load.f16.ll

affa1b1c - AMDGPU/GISel: Factor out AMDGPURegisterBankInfo::buildReadFirstLane

Tue, 10 May 2022 15:10:36 +0000

AMDGPU/GISel: Factor out AMDGPURegisterBankInfo::buildReadFirstLaneA later change will add a 3rd user, so factoring out the common codeseems useful.Reorganizing the executeInWaterfallLoop causes some more COPYs to begenerated, but those all fold away during instruction selection.Generating the comparisons uses generic instructions over machineinstructions now which admittedly shouldn't make a difference(though it should make it easier to move the waterfall loop generationto another place).(Resubmit with missing test added.)Differential Revision: https://reviews.llvm.org/D125324 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll

afc90101 - Revert "AMDGPU/GISel: Factor out AMDGPURegisterBankInfo::buildReadFirstLane"

Wed, 25 May 2022 17:03:23 +0000

Revert "AMDGPU/GISel: Factor out AMDGPURegisterBankInfo::buildReadFirstLane"This reverts commit 2a28467e5389c4d741d1825fadd39ae84ecaa5dc. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll

2a28467e - AMDGPU/GISel: Factor out AMDGPURegisterBankInfo::buildReadFirstLane

Tue, 10 May 2022 15:10:36 +0000

AMDGPU/GISel: Factor out AMDGPURegisterBankInfo::buildReadFirstLaneA later change will add a 3rd user, so factoring out the common codeseems useful.Reorganizing the executeInWaterfallLoop causes some more COPYs to begenerated, but those all fold away during instruction selection.Generating the comparisons uses generic instructions over machineinstructions now which admittedly shouldn't make a difference(though it should make it easier to move the waterfall loop generationto another place).Differential Revision: https://reviews.llvm.org/D125324 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll

18ed279a - [AMDGPU] gfx11 subtarget features & early tests

Thu, 14 Apr 2022 13:32:59 +0000

[AMDGPU] gfx11 subtarget features & early testsTablegen definitions for subtarget features and cpp predicate functions toaccess the features.New Sub-TargetProcessors and common latencies.Simple changes to MIR codegen tests which pass on gfx11 because they have thesame output as previous subtargets or operate on pseudo instructions whichare reused from previous subtargets.Contributors:Jay Foad Petar Avramovic Patch 4/N for upstreaming of AMDGPU gfx11 architectureDepends on D124538Reviewed By: Petar.Avramovic, foadDifferential Revision: https://reviews.llvm.org/D125261 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll

1f52d02c - [AMDGPU] Split waterfall loop exec manipulation

Mon, 28 Mar 2022 08:30:09 +0000

[AMDGPU] Split waterfall loop exec manipulationSplit waterfall loops into multiple blocks so that exec maskmanipulation (s_and_saveexec) does not occur in the middle ofa block.VGPR live range optimizer is updated to handle waterfall loopsspanning multiple blocks.Reviewed By: ruilingDifferential Revision: https://reviews.llvm.org/D122200 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll

bd2c01e9 - AMDGPU/GlobalISel: Do not use terminator copy before waterfall loops

Tue, 11 Jan 2022 19:15:48 +0000

AMDGPU/GlobalISel: Do not use terminator copy before waterfall loopsStop using the _term variants of the mov to save the initial execvalue before the waterfall loop. This cannot be glued to the bottom ofthe block because we may need to spill the result register. Just use aregular mov, like the loops produced on the DAG path. Fixes someverification errors with regalloc fast. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll

0cf860ec - AMDGPU/GlobalISel: Regenerate baseline checks to include -NEXT

Tue, 11 Jan 2022 20:28:44 +0000

AMDGPU/GlobalISel: Regenerate baseline checks to include -NEXT List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll

fd1cfc90 - [AMDGPU][GlobalISel] Fix waterfall loops

Thu, 28 Oct 2021 08:29:06 +0000

[AMDGPU][GlobalISel] Fix waterfall loops- Move the `s_and exec` to its correct position before the content of the waterfall loop- Use the SI_WATERFALL pseudo instruction, like for sdag, to benefit from optimizations- Add support for indirect function callsTo support indirect calls, add a G_SI_CALL instruction without registerclass restrictions and insert a waterfall loop when applying registerbanks.Differential Revision: https://reviews.llvm.org/D109052 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll

59f68652 - [AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset

Wed, 21 Jul 2021 14:53:59 +0000

[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offsetCodegen for the raw/struct buffer access intrinsics would update theoffset in the MMO to reflect the combined offset, if it was known to beconstant. If the combined offset was not known to be constant, or ifthere was an index, it would set the offset in the MMO to 0. This isunsafe because it makes it look like the access does not alias withanother access with a fixed non-zero offset.Fix these cases by setting the pointer in the MMO to null, to reflectthe fact that we do not have any known IR value pointer + constantoffset for the access.D106284 did this for SelectionDAG. This is the corresponding fix forGlobalISel.Differential Revision: https://reviews.llvm.org/D106451 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll

fae05692 - CodeGen: Print/parse LLTs in MachineMemOperands

Thu, 20 May 2021 02:25:51 +0000

CodeGen: Print/parse LLTs in MachineMemOperandsThis will currently accept the old number of bytes syntax, and convertit to a scalar. This should be removed in the near future (I think Iconverted all of the tests already, but likely missed a few).Not sure what the exact syntax and policy should be. We can continueprinting the number of bytes for non-generic instructions to avoidtest churn and only allow non-scalar types for generic instructions.This will currently print the LLT in parentheses, but accept parsingthe existing integers and implicitly converting to scalar. Theparentheses are a bit ugly, but the parser logic seems unable to dealwithout either parentheses or some keyword to indicate the start of atype. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll

3bffb1cd - [AMDGPU] Use single cache policy operand

Tue, 09 Feb 2021 00:36:10 +0000

[AMDGPU] Use single cache policy operandReplace individual operands GLC, SLC, and DLC with a single cache_policybitmask operand. This will reduce the number of operands in MIR and I hopethe amount of code. These operands are mostly 0 anyway.Additional advantage that parser will accept these flags in any order unlikenow.Differential Revision: https://reviews.llvm.org/D96469 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll

62d946e1 - GlobalISel: Merge some AMDGPU ABI lowering code to generic code

Sun, 07 Feb 2021 17:12:31 +0000

GlobalISel: Merge some AMDGPU ABI lowering code to generic codeAMDGPU currently has a lot of pre-processing code to pre-splitargument types into 32-bit pieces before passing it to the genericcode in handleAssignments. This is a bit sloppy and also requires someoverly fancy iterator work when building the calls. It's better if allargument marshalling code is handled directly inhandleAssignments. This handles more situations like decomposing largeelement vectors into sub-element sized pieces.This should mostly be NFC, but does change the generated code byshifting where the initial argument packing instructions are placed. Ithink this is nicer looking, since it now emits the packing codedirectly after the relevant copies, rather than after the copies forthe remaining arguments.This doubles down on gfx6/gfx7 using the gfx8+ ABI for 16-bittypes. This is ultimately the better option, but incompatible with theDAG. Fixing this requires more work, especially for f16. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll

a8d9d507 - [AMDGPU] gfx90a support

Wed, 17 Feb 2021 21:37:46 +0000

[AMDGPU] gfx90a supportDifferential Revision: https://reviews.llvm.org/D96906 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll

2291bd13 - [AMDGPU] Update subtarget features for new target ID support

Mon, 30 Nov 2020 17:06:35 +0000

[AMDGPU] Update subtarget features for new target ID supportSupport for XNACK and SRAMECC is not static on some GPUs. We must be ableto differentiate between different scenarios for these dynamic subtargetfeatures.The possible settings are:- Unsupported: The GPU has no support for XNACK/SRAMECC.- Any: Preference is unspecified. Use conservative settings that can run anywhere.- Off: Request support for XNACK/SRAMECC Off- On: Request support for XNACK/SRAMECC OnGCNSubtarget will track the four options based on the following criteria. Ifthe subtarget does not support XNACK/SRAMECC we say the setting is"Unsupported". If no subtarget features for XNACK/SRAMECC are requested wemust support "Any" mode. If the subtarget features XNACK/SRAMECC exist in thefeature string when initializing the subtarget, the settings are "On/Off".The defaults are updated to be conservatively correct, meaning if no settingfor XNACK or SRAMECC is explicitly requested, defaults will be used whichgenerate code that can be run anywhere. This corresponds to the "Any" setting.Differential Revision: https://reviews.llvm.org/D85882 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll

8214982b - [AMDGPU] Implement mir parseCustomPseudoSourceValue

Thu, 21 Jan 2021 17:12:27 +0000

[AMDGPU] Implement mir parseCustomPseudoSourceValueAllow parsing generated mir with custom pseudo source value tokens.Also rename pseudo source values to have more meaningful names.Relands ba7dcd8542ab, which had memory leaks.Differential Revision: https://reviews.llvm.org/D95215 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll

4dbdff66 - Revert "[AMDGPU] Implement mir parseCustomPseudoSourceValue"

Thu, 21 Jan 2021 17:11:48 +0000

Revert "[AMDGPU] Implement mir parseCustomPseudoSourceValue"This reverts commit ba7dcd8542abfc784255efcb0767701dec42fe83.(caused memory leaks) List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll

ba7dcd85 - [AMDGPU] Implement mir parseCustomPseudoSourceValue

Fri, 15 Jan 2021 12:57:24 +0000

[AMDGPU] Implement mir parseCustomPseudoSourceValueAllow parsing generated mir with custom pseudo source value tokens.Also rename pseudo source values to have more meaningful names.Differential Revision: https://reviews.llvm.org/D94768 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll

dfa9420f - AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR

Sat, 04 Jan 2020 20:35:26 +0000

AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTORIf we have s_pack_* instructions, legalize this toG_BUILD_VECTOR_TRUNC from s32 elements. This is closer to how how thes_pack_* instructions really behave.If we don't have s_pack_ instructions, expand this by creating a mergeto s32 and bitcasting. This expands to the expected bit operations. Ithink this eventually should go in a new bitcast legalize action typein LegalizerHelper.We already directly emit the shift operations in RegBankSelect for thevector case. This could possibly be cleaned up, but I also may want todefer doing this expansion to selection anyway. I'll see about thatwhen I try to actually match VOP3P instructions.This breaks the selection of the build_vector since tablegen doesn'tknow how to match G_BUILD_VECTOR_TRUNC yet, so just xfail it for now. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll

75d66f84 - AMDGPU/GlobalISel: Select llvm.amdcn.struct.tbuffer.load

Tue, 14 Jan 2020 01:06:26 +0000

AMDGPU/GlobalISel: Select llvm.amdcn.struct.tbuffer.load List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll