en Copyright 2015 Java http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll#3a205977 [amdgpu] Implement lds kernel id intrinsicImplement an intrinsic for use lowering LDS variables to differentaddresses from different kernels. This will allow kernels that cannotreach an LDS variable to avoid wasting space for it.There are a number of implicit arguments accessed by intrinsic alreadyso this implementation closely follows the existing handling. It is slightlynovel in that this SGPR is written by the kernel prologue.It is necessary in the general case to put variables at different addressessuch that they can be compactly allocated and thus necessary for anindirect function call to have some means of determining where agiven variable was allocated. Claiming an arbitrary SGPR into whichan integer can be written by the kernel, in this implementation basedon metadata associated with that kernel, which is then passed on toindirect call sites is sufficient to determine the variable address.The intent is to emit a __const array of LDS addresses and index into it.Reviewed By: arsenmDifferential Revision: https://reviews.llvm.org/D125060 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll Tue, 19 Jul 2022 16:46:17 +0000 Jon Chesterfield <jonathanchesterfield@gmail.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll#2d43955c [AMDGPU][NFC] Refactor AMDGPUCallingConv.tdRename CalleeSavedRegs defs to avoid being overly specific:* CSR_AMDGPU_AGPRs_32_255 => CSR_AMDGPU_AGPRs* CSR_AMDGPU_SGPRs_30_31 + CSR_AMDGPU_SGPRs_32_105 => CSR_AMDGPU_SGPRs* CSR_AMDGPU_SI_Gfx_SGPRs_4_29 + CSR_AMDGPU_SI_Gfx_SGPRs_64_105 => CSR_AMDGPU_SI_Gfx_SGPRs* CSR_AMDGPU_HighRegs => CSR_AMDGPU* CSR_AMDGPU_HighRegs_With_AGPRs => CSR_AMDGPU_GFX90AInsts* CSR_AMDGPU_SI_Gfx_With_AGPRs => CSR_AMDGPU_SI_Gfx_GFX90AInstsIntroduce a class RegMask to mark the cases where we use theCalleeSavedRegs class purely as an expedient way to produce a mask.Update the names of these masks to not mention "CSR". Other targets alsoseem to do this, so a reasonable alternative is to actually updatetable-gen to include a new class to do this explicitly, but the currentapproach seems harmless so I opted to just make it more explicit.Reviewed By: arsenm, sebastian-neDifferential Revision: https://reviews.llvm.org/D109008 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll Wed, 25 May 2022 17:17:53 +0000 Scott Linder <Scott.Linder@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll#04fff547 [AMDGPU] Move call clobbered return address registers s[30:31] to callee saved rangeCurrently the return address ABI registers s[30:31], which fall in the callclobbered register range, are added as a live-in on the function entry topreserve its value when we have calls so that it gets saved and restoredaround the calls.But the DWARF unwind information (CFI) needs to track where the return addressresides in a frame and the above approach makes it difficult to track thereturn address when the CFI information is emitted during the frame lowering,due to the involvment of understanding the control flow.This patch moves the return address ABI registers s[30:31] into callee savedregisters range and stops adding live-in for return address registers, so thatthe CFI machinery will know where the return address resides when CSRsave/restore happen during the frame lowering.And doing the above poses an issue that now the return instruction uses undefinedregister `sgpr30_sgpr31`. This is resolved by hiding the return address registeruse by the return instruction through the `SI_RETURN` pseudo instruction, whichdoesn't take any input operands, until the `SI_RETURN` pseudo gets lowered to the`S_SETPC_B64_return` during the `expandPostRAPseudo()`.As an added benefit, this patch simplifies overall return instruction handling.Note: The AMDGPU CFI changes are there only in the downstream code and anotherversion of this patch will be posted for review for the downstream code.Reviewed By: arsenm, ronliebDifferential Revision: https://reviews.llvm.org/D114652 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll Mon, 07 Mar 2022 19:39:18 +0000 Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu@amd.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll#0ba4e4b5 GlobalISel: Pass DebugLoc to getFunctionLiveInPhysRegFixes crash in assertion about dropping debug info. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll Sun, 09 Jan 2022 15:25:36 +0000 Matt Arsenault <Matthew.Arsenault@amd.com>