Changes in select-vector-shift.mir

40e75caf - [AArch64][GlobalISel] Fix incorrect codegen for <16 x s8> G_ASHR.

Fri, 09 Apr 2021 17:39:59 +0000

[AArch64][GlobalISel] Fix incorrect codegen for <16 x s8> G_ASHR.Fixes PR49904 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir

5c26be21 - [AArch64][GlobalISel] Lower G_BUILD_VECTOR -> G_DUP

Mon, 01 Mar 2021 19:58:07 +0000

[AArch64][GlobalISel] Lower G_BUILD_VECTOR -> G_DUPIf we have```%vec = G_BUILD_VECTOR %reg, %reg, ..., %reg```Then lower it to```%vec = G_DUP %reg```Also update the selector to handle constant splats on G_DUP.This will not combine when the splat is all zeros or ones. Tablegen-importedpatterns rely on these being G_BUILD_VECTOR.Minor code size improvements on CTMark at -Os.Also adds some utility functions to make it a bit easier to recognize splats,and an AArch64-specific splat helper.Differential Revision: https://reviews.llvm.org/D97731 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir

2dba5461 - [AArch64][GlobalISel] Add a few more vector type combinations for shift selection.

Sat, 26 Sep 2020 00:21:03 +0000

[AArch64][GlobalISel] Add a few more vector type combinations for shift selection. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir

e3f5046e - [AArch64][GlobalISel] Merge selection of vector-vector G_ASHR/G_LSHR and support more cases.

Mon, 21 Sep 2020 22:28:04 +0000

[AArch64][GlobalISel] Merge selection of vector-vector G_ASHR/G_LSHR and support more cases.The vector-immediate cases are handled elsewhere in an earlier commit. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir

a513fdec - [AArch64][GlobalISel] Add a post-legalize combine for lowering vector-immediate G_ASHR/G_LSHR.

Mon, 21 Sep 2020 22:03:29 +0000

[AArch64][GlobalISel] Add a post-legalize combine for lowering vector-immediate G_ASHR/G_LSHR.In order to select the immediate forms using the imported patterns, we need tolower them into new G_VASHR/G_VLSHR target generic ops. Add a combine to do thismatching build_vector of constant operands.With this, we get selection for free. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir

5a50f8b3 - [AArch64][GlobalISel] Add legalization and selection support for <4 x s16> G_SHL.

Sat, 19 Sep 2020 06:31:30 +0000

[AArch64][GlobalISel] Add legalization and selection support for <4 x s16> G_SHL. List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir

fceadbcb - [AArch64][GlobalISel] Improve codegen for some constant vectors by using constant pool loads.

Mon, 22 Jun 2020 23:25:49 +0000

[AArch64][GlobalISel] Improve codegen for some constant vectors by using constant pool loads.There's more smarts in AArch64ISelLowering that we don't have yet, but thischange incrementally improves some of the more common patterns. I think futureiterations will want to use some combination of PostLegalizerCombiner and theselector to catch the other cases.Differential Revision: https://reviews.llvm.org/D82340 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir

c77b4411 - [AArch64][GlobalISel] Add support for selection of vector G_SHL with immediates.

Fri, 06 Dec 2019 21:42:13 +0000

[AArch64][GlobalISel] Add support for selection of vector G_SHL with immediates.Only implemented for the type combinations already supported for G_SHL.Differential Revision: https://reviews.llvm.org/D71153 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir

9c7d599d - [AArch64][GlobalISel] Implement selection for G_SHL of <2 x i64>

Sat, 21 Sep 2019 09:21:16 +0000

[AArch64][GlobalISel] Implement selection for G_SHL of <2 x i64>Simple continuation of existing selection support.llvm-svn: 372467 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir

a59a8868 - [AArch64][GlobalISel] Selection support for G_ASHR of <2 x s64>

Sat, 21 Sep 2019 09:21:13 +0000

[AArch64][GlobalISel] Selection support for G_ASHR of <2 x s64>Just add an extra case to the existing selection logic.llvm-svn: 372466 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir

48904e94 - [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing

Wed, 11 Sep 2019 11:16:48 +0000

[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsingSummary:This catches malformed mir files which specify alignment as log2 instead of pow2.See https://reviews.llvm.org/D65945 for reference,This is patch is part of a series to introduce an Alignment type.See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.htmlSee this patch for the introduction of the type: https://reviews.llvm.org/D64790Reviewers: courbetSubscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commitsTags: #llvmDifferential Revision: https://reviews.llvm.org/D67433llvm-svn: 371608 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir

9bf092d7 - [AArch64][GlobalISel] Add isel support for vector G_ICMP and G_ASHR & G_SHL

Tue, 09 Apr 2019 21:22:43 +0000

[AArch64][GlobalISel] Add isel support for vector G_ICMP and G_ASHR & G_SHLThe selection for G_ICMP is unfortunately not currently importable from SDAGdue to the use of custom SDNodes. To support this, this selection method has anopcode table which has been generated by a script, indexed by variousinstruction properties. Ideally in future we will have a GISel native selectionpatterns that we can write in tablegen to improve on this.For selection of some types we also need support for G_ASHR and G_SHL which aregenerated as a result of legalization. This patch also adds support for them,generating the same code as SelectionDAG currently does.Differential Revision: https://reviews.llvm.org/D60436llvm-svn: 358035 List of files: /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir