Changes in vector-select.ll

37fa99ed - [SchedModels][CortexA55] Add ASIMD integer instructions

Thu, 17 Feb 2022 10:41:57 +0000

[SchedModels][CortexA55] Add ASIMD integer instructionsDepends on D114642Original review https://reviews.llvm.org/D112201OS Laboratory. Huawei Russian Research Institute. Saint-PetersburgReviewed By: dmgreenDifferential Revision: https://reviews.llvm.org/D117003 List of files: /llvm-project-15.0.7/llvm/test/Analysis/CostModel/AArch64/vector-select.ll

15ba588d - [test] Migrate '-analyze -cost-model' to '-passes=print'

Wed, 09 Feb 2022 23:25:18 +0000

[test] Migrate '-analyze -cost-model' to '-passes=print' List of files: /llvm-project-15.0.7/llvm/test/Analysis/CostModel/AArch64/vector-select.ll

17ebd68a - [AArch64] Fix costs of float vector compare/selects pairs.

Mon, 31 Jan 2022 10:18:28 +0000

[AArch64] Fix costs of float vector compare/selects pairs.The current cost-model overestimates the cost of vector compares &selects for ordered floating point compares. This patch fixes that byextending the existing logic for integer predicates.Reviewed By: dmgreenDifferential Revision: https://reviews.llvm.org/D118256 List of files: /llvm-project-15.0.7/llvm/test/Analysis/CostModel/AArch64/vector-select.ll

cb3df1a2 - [AArch64] Add vector compare/select tests with UNE predicate.

Thu, 27 Jan 2022 14:20:30 +0000

[AArch64] Add vector compare/select tests with UNE predicate.Precommit some additional tests for D118256. List of files: /llvm-project-15.0.7/llvm/test/Analysis/CostModel/AArch64/vector-select.ll

e6ebd2c7 - [AArch64] Add float vector compare/select cost-model tests.

Wed, 26 Jan 2022 16:26:19 +0000

[AArch64] Add float vector compare/select cost-model tests. List of files: /llvm-project-15.0.7/llvm/test/Analysis/CostModel/AArch64/vector-select.ll

61bb8b5d - [AArch64] Convert sra(X, elt_size(X)-1) to cmlt(X, 0)

Tue, 14 Dec 2021 15:29:44 +0000

[AArch64] Convert sra(X, elt_size(X)-1) to cmlt(X, 0)CMLT has twice the execution throughput of SSHR on Arm out-of-order cores.Differential Revision: https://reviews.llvm.org/D115457 List of files: /llvm-project-15.0.7/llvm/test/Analysis/CostModel/AArch64/vector-select.ll

adec9223 - [AArch64] Make -mcpu=generic schedule for an in-order core

Sat, 09 Oct 2021 14:58:31 +0000

[AArch64] Make -mcpu=generic schedule for an in-order coreWe would like to start pushing -mcpu=generic towards enabling the set offeatures that improves performance for some CPUs, without hurting anyothers. A blend of the performance options hopefully beneficial to allCPUs. The largest part of that is enabling in-order scheduling using theCortex-A55 schedule model. This is similar to the Arm backend changefrom eecb353d0e25ba which made -mcpu=generic perform in-order schedulingusing the cortex-a8 schedule model.The idea is that in-order cpu's require the most help in instructionscheduling, whereas out-of-order cpus can for the most part out-of-orderschedule around different codegen. Our benchmarking suggests thathypothesis holds. When running on an in-order core this improvedperformance by 3.8% geomean on a set of DSP workloads, 2% geomean onsome other embedded benchmark and between 1% and 1.8% on a set ofsinglecore and multicore workloads, all running on a Cortex-A55 cluster.On an out-of-order cpu the results are a lot more noisy but show flatperformance or an improvement. On the set of DSP and embeddedbenchmarks, run on a Cortex-A78 there was a very noisy 1% speedimprovement. Using the most detailed results I could find, SPEC2006 runson a Neoverse N1 show a small increase in instruction count (+0.127%),but a decrease in cycle counts (-0.155%, on average). The instructioncount is very low noise, the cycle count is more noisy with a 0.15%decrease not being significant. SPEC2k17 shows a small decrease (-0.2%)in instruction count leading to a -0.296% decrease in cycle count. Theseresults are within noise margins but tend to show a small improvement ingeneral.When specifying an Apple target, clang will set "-target-cpu apple-a7"on the command line, so should not be affected by this change whenrunning from clang. This also doesn't enable more runtime unrolling like-mcpu=cortex-a55 does, only changing the schedule used.A lot of existing tests have updated. This is a summary of the importantdifferences: - Most changes are the same instructions in a different order. - Sometimes this leads to very minor inefficiencies, such as requiring an extra mov to move variables into r0/v0 for the return value of a test function. - misched-fusion.ll was no longer fusing the pairs of instructions it should, as per D110561. I've changed the schedule used in the test for now. - neon-mla-mls.ll now uses "mul; sub" as opposed to "neg; mla" due to the different latencies. This seems fine to me. - Some SVE tests do not always remove movprfx where they did before due to different register allocation giving different destructive forms. - The tests argument-blocks-array-of-struct.ll and arm64-windows-calls.ll produce two LDR where they previously produced an LDP due to store-pair-suppress kicking in. - arm64-ldp.ll and arm64-neon-copy.ll are missing pre/postinc on LPD. - Some tests such as arm64-neon-mul-div.ll and ragreedy-local-interval-cost.ll have more, less or just different spilling. - In aarch64_generated_funcs.ll.generated.expected one part of the function is no longer outlined. Interestingly if I switch this to use any other scheduled even less is outlined.Some of these are expected to happen, such as differences in outliningor register spilling. There will be places where these result in worsecodegen, places where they are better, with the SPEC instruction countssuggesting it is not a decrease overall, on average.Differential Revision: https://reviews.llvm.org/D110830 List of files: /llvm-project-15.0.7/llvm/test/Analysis/CostModel/AArch64/vector-select.ll

b3b993a7 - Reland "[TTI] Add VecPred argument to getCmpSelInstrCost."

Mon, 02 Nov 2020 12:40:34 +0000

Reland "[TTI] Add VecPred argument to getCmpSelInstrCost."This reverts the revert commit 408c4408facc3a79ee4ff7e9983cc972f797e176.This version of the patch includes a fix for a crash caused bytreating ICmp/FCmp constant expressions as instructions.Original message:On some targets, like AArch64, vector selects can be efficiently loweredif the vector condition is a compare with a supported predicate.This patch adds a new argument to getCmpSelInstrCost, to indicate thepredicate of the feeding select condition. Note that it is notsufficient to use the context instruction when querying the cost of avector select starting from a scalar one, because the condition of thevector select could be composed of compares with different predicates.This change greatly improves modeling the costs of certaincompare/select patterns on AArch64.I am also planning on putting up patches to make use of the new argument inSLPVectorizer & LV. List of files: /llvm-project-15.0.7/llvm/test/Analysis/CostModel/AArch64/vector-select.ll

408c4408 - Revert "[TTI] Add VecPred argument to getCmpSelInstrCost."

Fri, 30 Oct 2020 21:19:52 +0000

Revert "[TTI] Add VecPred argument to getCmpSelInstrCost."This reverts commit 73f01e3df58dca9d1596440b866b52929e3878de.This appears to breakhttp://lab.llvm.org:8011/#/builders/85/builds/383. List of files: /llvm-project-15.0.7/llvm/test/Analysis/CostModel/AArch64/vector-select.ll

73f01e3d - [TTI] Add VecPred argument to getCmpSelInstrCost.

Fri, 30 Oct 2020 13:48:28 +0000

[TTI] Add VecPred argument to getCmpSelInstrCost.On some targets, like AArch64, vector selects can be efficiently loweredif the vector condition is a compare with a supported predicate.This patch adds a new argument to getCmpSelInstrCost, to indicate thepredicate of the feeding select condition. Note that it is notsufficient to use the context instruction when querying the cost of avector select starting from a scalar one, because the condition of thevector select could be composed of compares with different predicates.This change greatly improves modeling the costs of certaincompare/select patterns on AArch64.I am also planning on putting up patches to make use of the new argument inSLPVectorizer & LV.Reviewed By: dmgreen, RKSimonDifferential Revision: https://reviews.llvm.org/D90070 List of files: /llvm-project-15.0.7/llvm/test/Analysis/CostModel/AArch64/vector-select.ll

066737fd - [AArch64] Remove AArch64ISD::NOT, use vnot instead

Wed, 28 Oct 2020 08:15:37 +0000

[AArch64] Remove AArch64ISD::NOT, use vnot insteadvnot (xor -1) should be equivalent to the AArch64 specific AArch64ISD::NOTnode, but allow more folding thanks to all the target independentoptimizations. Specifically this allows select(icmp ne, x, y) tobecome "cmeq; bsl y, x" as opposed to needing to convert the predicatewith "cmeq; mvn; bsl x, y"Unfortunately there is a regression in a cmtst test, but the code itselected from was already non-canonical, with instcombine preferring touse an eq predicate instead. Plus the more common case of icmp ne isimproved.Differential Revision: https://reviews.llvm.org/D90126 List of files: /llvm-project-15.0.7/llvm/test/Analysis/CostModel/AArch64/vector-select.ll

089c1ccd - [AArch64] Add vector compare/select cost-model tests.

Fri, 23 Oct 2020 18:42:16 +0000

[AArch64] Add vector compare/select cost-model tests. List of files: /llvm-project-15.0.7/llvm/test/Analysis/CostModel/AArch64/vector-select.ll