Changes in X86MCInstLower.cpp

3e0bf1c7 - [CodeGen] Move instruction predicate verification to emitInstruction

Thu, 14 Jul 2022 08:33:28 +0000

[CodeGen] Move instruction predicate verification to emitInstructionD25618 added a method to verify the instruction predicates for anemitted instruction, through verifyInstructionPredicates added intoMCCodeEmitter::encodeInstruction. This is a very useful idea,but the implementation inside MCCodeEmitter made it only fire for objectfiles, not assembly which most of the llvm test suite uses.This patch moves the code into the _MC::verifyInstructionPredicatesmethod, inside the InstrInfo. The allows it to be called from otherplaces, such as in this patch where it is called from theAsmPrinter::emitInstruction methods which should trigger forboth assembly and object files. It can also be called from other placessuch as verifyInstruction, but that is not done here (it tends to catcherrors earlier, but in reality just shows all the mir tests that haveincorrect feature predicates). The interface was also simplifiedslightly, moving computeAvailableFeatures into the function so that itdoes not need to be called externally.The ARM, AMDGPU (but not R600), AVR, Mips and X86 backends all currentlyshow errors in the test-suite, so have been disabled with FIXMEcomments.Recommitted with some fixes for the leftover MCII variables in releasebuilds.Differential Revision: https://reviews.llvm.org/D129506 List of files: /llvm-project-15.0.7/llvm/lib/Target/X86/X86MCInstLower.cpp

95252133 - Revert "Move instruction predicate verification to emitInstruction"

Wed, 13 Jul 2022 12:28:11 +0000

Revert "Move instruction predicate verification to emitInstruction"This reverts commit e2fb8c0f4b940e0285ee36c112469fa75d4b60ff as it doesnot build for Release builds, and some buildbots are giving more warningthan I saw locally. Reverting to fix those issues. List of files: /llvm-project-15.0.7/llvm/lib/Target/X86/X86MCInstLower.cpp

e2fb8c0f - Move instruction predicate verification to emitInstruction

Wed, 13 Jul 2022 11:53:32 +0000

Move instruction predicate verification to emitInstructionD25618 added a method to verify the instruction predicates for anemitted instruction, through verifyInstructionPredicates added intoMCCodeEmitter::encodeInstruction. This is a very useful idea,but the implementation inside MCCodeEmitter made it only fire for objectfiles, not assembly which most of the llvm test suite uses.This patch moves the code into the _MC::verifyInstructionPredicatesmethod, inside the InstrInfo. The allows it to be called from otherplaces, such as in this patch where it is called from theAsmPrinter::emitInstruction methods which should trigger forboth assembly and object files. It can also be called from other placessuch as verifyInstruction, but that is not done here (it tends to catcherrors earlier, but in reality just shows all the mir tests that haveincorrect feature predicates). The interface was also simplifiedslightly, moving computeAvailableFeatures into the function so that itdoes not need to be called externally.The ARM, AMDGPU (but not R600), AVR, Mips and X86 backends all currentlyshow errors in the test-suite, so have been disabled with FIXMEcomments.Differential Revision: https://reviews.llvm.org/D129506 List of files: /llvm-project-15.0.7/llvm/lib/Target/X86/X86MCInstLower.cpp

7a47ee51 - [llvm] Don't use Optional::getValue (NFC)

Tue, 21 Jun 2022 05:45:45 +0000

[llvm] Don't use Optional::getValue (NFC) List of files: /llvm-project-15.0.7/llvm/lib/Target/X86/X86MCInstLower.cpp

9ee15bba - [MC] Lower case the first letter of EmitCOFF* EmitWin* EmitCV*. NFC

Thu, 26 May 2022 07:14:08 +0000

[MC] Lower case the first letter of EmitCOFF* EmitWin* EmitCV*. NFC List of files: /llvm-project-15.0.7/llvm/lib/Target/X86/X86MCInstLower.cpp

3337f506 - [X86] Fix handling of maskmovdqu in x32 differently

Tue, 12 Apr 2022 17:32:14 +0000

[X86] Fix handling of maskmovdqu in x32 differentlyThis reverts the functional changes of D103427 but keeps its tests, andand reimplements the functionality by reusing the existing 32-bitMASKMOVDQU and VMASKMOVDQU instructions as suggested by skan in review.These instructions were previously predicated on Not64BitMode. Thisreimplementation restores the disassembly of a class of instructions,which will see a test added in followup patch D122449.These instructions are in 64-bit mode special cased inX86MCInstLower::Lower, because we use flags with one meaning for subtlydifferent things: we have an AdSize32 class which indicates both thatthe instruction needs a 0x67 prefix and that the text form of theinstruction implies a 0x67 prefix. These instructions are special inneeding a 0x67 prefix but having a text form that does *not* imply a0x67 prefix, so we encode this in MCInst as an instruction that has anexplicit address size override.Note that originally VMASKMOVDQU64 was special cased to be excluded fromdisassembly, as we cannot distinguish between VMASKMOVDQU andVMASKMOVDQU64 and rely on the fact that these are indistinguishable, orclose enough to it, at the MCInst level that it does not matter which weuse. Because VMASKMOVDQU now receives special casing, even though itdoes not make a difference in the current implementation, as aprecaution VMASKMOVDQU is excluded from disassembly rather thanVMASKMOVDQU64.Reviewed By: RKSimon, skanDifferential Revision: https://reviews.llvm.org/D122540 List of files: /llvm-project-15.0.7/llvm/lib/Target/X86/X86MCInstLower.cpp

de88c1ab - [asan][X86] Change some std::string variables to StringRef. NFC

Thu, 03 Feb 2022 00:34:35 +0000

[asan][X86] Change some std::string variables to StringRef. NFC List of files: /llvm-project-15.0.7/llvm/lib/Target/X86/X86MCInstLower.cpp

d87e6170 - Teach the backend to make references to swift_async_extendedFramePointerFlags weak if it emits it

Mon, 13 Dec 2021 20:33:15 +0000

Teach the backend to make references to swift_async_extendedFramePointerFlags weak if it emits itWhen references to the symbol `swift_async_extendedFramePointerFlags`are emitted they have to be weak.References to the symbol `swift_async_extendedFramePointerFlags` getemitted only by frame lowering code. Therefore, the backend needs to trackreferences to the symbol and mark them weak.Differential Revision: https://reviews.llvm.org/D115672 List of files: /llvm-project-15.0.7/llvm/lib/Target/X86/X86MCInstLower.cpp

89577be8 - [ASan] Replace IR based callbacks with shared assembly code callbacks.

Mon, 13 Dec 2021 16:10:58 +0000

[ASan] Replace IR based callbacks with shared assembly code callbacks.This change moves optimized callbacks from each .o file to compiler-rt.Reviewed By: vitalybuka, morehouseDifferential Revision: https://reviews.llvm.org/D115396 List of files: /llvm-project-15.0.7/llvm/lib/Target/X86/X86MCInstLower.cpp

a55e51f9 - Revert "[ASan] Replace IR based callbacks with shared assembly code callbacks."

Sat, 11 Dec 2021 00:40:04 +0000

Revert "[ASan] Replace IR based callbacks with shared assembly code callbacks."This reverts commit db124df4950699caa020384ee8da23af6c707d3c.Broke some builds:https://lab.llvm.org/buildbot/#/builders/98/builds/9895https://lab.llvm.org/buildbot/#/builders/91/builds/434Reviewed By: kstoimenovDifferential Revision: https://reviews.llvm.org/D115564 List of files: /llvm-project-15.0.7/llvm/lib/Target/X86/X86MCInstLower.cpp

db124df4 - [ASan] Replace IR based callbacks with shared assembly code callbacks.

Wed, 08 Dec 2021 21:24:10 +0000

021ecbbb - [ASan] Changed intrisic implemenation to use PLT safe registers.

Thu, 02 Dec 2021 22:15:01 +0000

[ASan] Changed intrisic implemenation to use PLT safe registers.Changed registers to R10 and R11 because PLT resolution clobbers them. Also changed the implementation to use R11 instead of RCX, which saves a push/pop.Reviewed By: vitalybukaDifferential Revision: https://reviews.llvm.org/D115002 List of files: /llvm-project-15.0.7/llvm/lib/Target/X86/X86MCInstLower.cpp

671f0930 - [X86] Selective relocation relaxation for +tagged-globals

Fri, 19 Nov 2021 14:12:51 +0000

[X86] Selective relocation relaxation for +tagged-globalsFor tagged-globals, we only need to disable relaxation for globals thatwe actually tag. With this patch function pointer relocations, whichwe do not instrument, can be relaxed.This patch also makes tagged-globals work properly with LTO, as-Wa,-mrelax-relocations=no doesn't work with LTO.Reviewed By: pccDifferential Revision: https://reviews.llvm.org/D113220 List of files: /llvm-project-15.0.7/llvm/lib/Target/X86/X86MCInstLower.cpp

d391e4fe - [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC

Sun, 07 Nov 2021 15:06:54 +0000

[X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFCBe more consistent in the naming convention for the various RET instructions to specify in terms of bitwidth.Helps prevent future scheduler model mismatches like those that were only addressed in D44687.Differential Revision: https://reviews.llvm.org/D113302 List of files: /llvm-project-15.0.7/llvm/lib/Target/X86/X86MCInstLower.cpp

89b57061 - Move TargetRegistry.(h|cpp) from Support to MC

Fri, 08 Oct 2021 17:48:15 +0000

Move TargetRegistry.(h|cpp) from Support to MCThis moves the registry higher in the LLVM library dependency stack.Every client of the target registry needs to link against MC anyway toactually use the target, so we might as well move this out of Support.This allows us to ensure that Support doesn't have includes from MC/*.Differential Revision: https://reviews.llvm.org/D111454 List of files: /llvm-project-15.0.7/llvm/lib/Target/X86/X86MCInstLower.cpp

3f875134 - [asan] Fixed the jump to use the 4 byte offset version.

Wed, 08 Sep 2021 17:04:43 +0000

[asan] Fixed the jump to use the 4 byte offset version.This should have been the 4 byte version in the first place. Unfortunatelly there is no easy way to add a test as both the 1 byte and 4 byte version are printed as 'jmp' in the assembly code.Reviewed By: kdaDifferential Revision: https://reviews.llvm.org/D109453 List of files: /llvm-project-15.0.7/llvm/lib/Target/X86/X86MCInstLower.cpp

5e71839f - [MC] Add MCSubtargetInfo to MCAlignFragment

Fri, 06 Aug 2021 16:42:12 +0000

[MC] Add MCSubtargetInfo to MCAlignFragmentIn preparation for passing the MCSubtargetInfo (STI) through to writeNopsso that it can use the STI in operation at the time, we need to record theSTI in operation when a MCAlignFragment may write nops as padding. TheSTI is currently unused, a further patch will pass it through towriteNops.There are many places that can create an MCAlignFragment, in most caseswe can find out the STI in operation at the time. In a few places thisisn't possible as we are in initialisation or finalisation, or areemitting constant pools. When possible I've tried to find the mostappropriate existing fragment to obtain the STI from, when none isavailable use the per module STI.For constant pools we don't actually need to use EmitCodeAlign as theconstant pools are data anyway so falling through into it via anexecutable NOP is no better than falling through into data padding.This is a prerequisite for D45962 which uses the STI to emit theappropriate NOP for the STI. Which can differ per fragment.Note that involves an interface change to InitSections. It is nowcalled initSections and requires a SubtargetInfo as a parameter.Differential Revision: https://reviews.llvm.org/D45961 List of files: /llvm-project-15.0.7/llvm/lib/Target/X86/X86MCInstLower.cpp

cf53c6c9 - [asan] Fixed link error by setting jump symbol to R_X86_64_PLT32.

Thu, 02 Sep 2021 19:26:54 +0000

[asan] Fixed link error by setting jump symbol to R_X86_64_PLT32.Fixing this link error:ld: error: relocation R_X86_64_PC32 cannot be used against symbol __asan_report_load...; recompile with -fPICReviewed By: vitalybukaDifferential Revision: https://reviews.llvm.org/D109183 List of files: /llvm-project-15.0.7/llvm/lib/Target/X86/X86MCInstLower.cpp

2e83a0ef - [asan] Fixed a runtime crash.

Thu, 26 Aug 2021 00:12:53 +0000

[asan] Fixed a runtime crash.Looks like the NoRegister has some effect on the final code that is generated. My guess is that some optimization kicks in at the end?When I use -S to dump the assembly I get the correct version with 'shrq $3, %r8': movq %r9, %r8 shrq $3, %r8 movsbl 2147450880(%r8), %r8dBut, when I disassemble the final binary I get RAX in stead of R8: mov %r9,%r8 shr $0x3,%rax movsbl 0x7fff8000(%r8),%r8dReviewed By: vitalybukaDifferential Revision: https://reviews.llvm.org/D108745 List of files: /llvm-project-15.0.7/llvm/lib/Target/X86/X86MCInstLower.cpp

47f2affa - Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI.

Thu, 26 Aug 2021 12:15:29 +0000

Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI. List of files: /llvm-project-15.0.7/llvm/lib/Target/X86/X86MCInstLower.cpp