Changes in X86InstPrinterCommon.cpp

6cfe41dc - [X86] Rename more target feature related things consistency. NFC

Fri, 18 Mar 2022 05:11:51 +0000

[X86] Rename more target feature related things consistency. NFC-Rename Mode*Bit to Is*Bit to match X86Subtarget.-Rename FeatureLAHFSAHF to FeatureLAFHSAFH64 to match X86Subtarget.-Use consistent capitalizationReviewed By: skanDifferential Revision: https://reviews.llvm.org/D121975 List of files: /llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp

1d371982 - [X86] Preserve redundant Address-Size override prefix

Fri, 25 Feb 2022 23:04:40 +0000

[X86] Preserve redundant Address-Size override prefixPrint and emit redundant Address-Size override prefix if it's set on theinstruction.Reviewed By: skanDifferential Revision: https://reviews.llvm.org/D120592 List of files: /llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp

f1de9d6d - [X86] AVX512FP16 instructions enabling 2/6

Sun, 15 Aug 2021 00:17:30 +0000

[X86] AVX512FP16 instructions enabling 2/6Enable FP16 binary operator instructions.Ref.: https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.htmlReviewed By: LuoYuankeDifferential Revision: https://reviews.llvm.org/D105264 List of files: /llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp

756f5978 - [X86] Support Intel avxvnni

Fri, 30 Oct 2020 04:58:05 +0000

[X86] Support Intel avxvnniThis patch mainly made the following changes:1. Support AVX-VNNI instructions;2. Introduce ExplicitVEXPrefix flag so that vpdpbusd/vpdpbusds/vpdpbusds/vpdpbusds instructions only use vex-encoding when user explicity add {vex} prefix.Differential Revision: https://reviews.llvm.org/D89105 List of files: /llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp

180548c5 - [X86] VEX/EVEX prefix doesn't work for inline assembly.

Fri, 23 Oct 2020 03:32:19 +0000

[X86] VEX/EVEX prefix doesn't work for inline assembly.For now, we lost the encoding information if we using inline assembly.The encoding for the inline assembly will keep default even if we addthe vex/evex prefix.Differential Revision: https://reviews.llvm.org/D90009 List of files: /llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp

819b2d9c - [llvm-objdump] Symbolize binary addresses for low-noisy asm diff.

Mon, 20 Jul 2020 16:45:32 +0000

[llvm-objdump] Symbolize binary addresses for low-noisy asm diff.When diffing disassembly dump of two binaries, I see lots of noises from mismatched jump target addresses and global data references, which unnecessarily causes diffs on every function, making it impractical. I'm trying to symbolize the raw binary addresses to minimize the diff noise.In this change, a local branch target is modeled as a label and the branch target operand will simply be printed as a label. Local labels are collected by a separate pre-decoding pass beforehand. A global data memory operand will be printed as a global symbol instead of the raw data address. Unfortunately, due to the way the disassembler is set up and to be less intrusive, a global symbol is always printed as the last operand of a memory access instruction. This is less than ideal but is probably acceptable from checking code quality point of view since on most targets an instruction can have at most one memory operand.So far only the X86 disassemblers are supported.Test Plan:llvm-objdump -d --x86-asm-syntax=intel --no-show-raw-insn --no-leading-addr :```Disassembly of section .text:<_start>: push rax mov dword ptr [rsp + 4], 0 mov dword ptr [rsp], 0 mov eax, dword ptr [rsp] cmp eax, dword ptr [rip + 4112] # 202182 jge 0x20117e <_start+0x25> call 0x201158 inc dword ptr [rsp] jmp 0x201169 <_start+0x10> xor eax, eax pop rcx ret```llvm-objdump -d **--symbolize-operands** --x86-asm-syntax=intel --no-show-raw-insn --no-leading-addr :```Disassembly of section .text:<_start>: push rax mov dword ptr [rsp + 4], 0 mov dword ptr [rsp], 0: mov eax, dword ptr [rsp] cmp eax, dword ptr jge call inc dword ptr [rsp] jmp : xor eax, eax pop rcx ret```Note that the jump instructions like `jge 0x20117e <_start+0x25>` without this work is printed as a real target address and an offset from the leading symbol. With a change in the optimizer that adds/deletes an instruction, the address and offset may shift for targets placed after the instruction. This will be a problem when diffing the disassembly from two optimizers where there are unnecessary false positives due to such branch target address changes. With `--symbolize-operand`, a label is printed for a branch target instead to reduce the false positives. Similarly, the disassemble of PC-relative global variable references is also prone to instruction insertion/deletion.Reviewed By: jhenderson, MaskRayDifferential Revision: https://reviews.llvm.org/D84191 List of files: /llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp

87de9a07 - [X86InstPrinter] Change printPCRelImm to print the target address in hexadecimal form

Sun, 22 Mar 2020 22:03:10 +0000

[X86InstPrinter] Change printPCRelImm to print the target address in hexadecimal form```// llvm-objdump -d output (before)400000: e8 0b 00 00 00 callq 11400005: e8 0b 00 00 00 callq 11// llvm-objdump -d output (after)400000: e8 0b 00 00 00 callq 0x400010400005: e8 0b 00 00 00 callq 0x400015// GNU objdump -d. The lack of 0x is not ideal because the result cannot be re-assembled400000: e8 0b 00 00 00 callq 400010400005: e8 0b 00 00 00 callq 400015```In llvm-objdump, we pass the address of the next MCInst. Ideally weshould just thread the address of the current address, unfortunately wecannot call X86MCCodeEmitter::encodeInstruction (X86MCCodeEmitterrequires MCInstrInfo and MCContext) to get the length of the MCInst.MCInstPrinter::printInst has other callers (e.g llvm-mc -filetype=asm, llvm-mca) which set Address to 0.They leave MCInstPrinter::PrintBranchImmAsAddress as false and this change is a no-op for them.Reviewed By: jhendersonDifferential Revision: https://reviews.llvm.org/D76580 List of files: /llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp

5fad05e8 - [MCInstPrinter] Pass `Address` parameter to MCOI::OPERAND_PCREL typed operands. NFC

Sun, 22 Mar 2020 19:32:27 +0000

[MCInstPrinter] Pass `Address` parameter to MCOI::OPERAND_PCREL typed operands. NFCFollow-up of D72172 and D72180This patch passes `uint64_t Address` to print methods of PC-relativeoperands so that subsequent target specific patches can change`*InstPrinter::print{Operand,PCRelImm,...}` to customize the output.Add MCInstPrinter::PrintBranchImmAsAddress which is set to true byllvm-objdump.```// Current llvm-objdump -d outputaarch64: 20000: bl #0ppc: 20000: bl .+4x86: 20000: callq 0// Ideal outputaarch64: 20000: bl 0x20000ppc: 20000: bl 0x20004x86: 20000: callq 0x20005// GNU objdump -d. The lack of 0x is not ideal because the result cannot be re-assembledaarch64: 20000: bl 20000ppc: 20000: bl 0x20004x86: 20000: callq 20005```In `lib/Target/X86/X86GenAsmWriter1.inc` (generated by `llvm-tblgen -gen-asm-writer`):``` case 12: // CALL64pcrel32, CALLpcrel16, CALLpcrel32, EH_SjLj_Setup, JCXZ, JECXZ, J...- printPCRelImm(MI, 0, O);+ printPCRelImm(MI, Address, 0, O); return;```Some targets have 2 `printOperand` overloads, one without `Address` andone with `Address`. They should annotate derived `Operand` properly with`let OperandType = "OPERAND_PCREL"`.Reviewed By: jhendersonDifferential Revision: https://reviews.llvm.org/D76574 List of files: /llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp

2e67d0c8 - [X86] Add VP2INTERSECT instructions

Fri, 31 May 2019 02:50:41 +0000

[X86] Add VP2INTERSECT instructionsSupport Intel AVX512 VP2INTERSECT instructions in llvmPatch by Xiang Zhang (xiangzhangllvm)Differential Revision: https://reviews.llvm.org/D62366llvm-svn: 362188 List of files: /llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp

b28b8b77 - [X86] Move InstPrinter files to MCTargetDesc. NFC

Fri, 10 May 2019 23:24:38 +0000

[X86] Move InstPrinter files to MCTargetDesc. NFCFor some targets, there is a circular dependency between InstPrinter andMCTargetDesc. Merging them together will fix this. For the other targets,the merging is to maintain consistency so all targets will have the samestructure.llvm-svn: 360484 List of files: /llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp