en Copyright 2015 Java http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZSchedule.td#9778ec05 [SystemZ] Add z16 scheduler descriptionAdd scheduler description for the new IBM z16 processor.Patch by Jonas Paulsson. List of files: /llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZSchedule.td Thu, 21 Apr 2022 18:38:16 +0000 Ulrich Weigand <ulrich.weigand@de.ibm.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZSchedule.td#819c1651 [SystemZ] Support z15 processor nameThe recently announced IBM z15 processor implements the architecturealready supported as "arch13" in LLVM. This patch adds support for"z15" as an alternate architecture name for arch13.The patch also uses z15 in a number of places where we used arch13as long as the official name was not yet announced.llvm-svn: 372435 List of files: /llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZSchedule.td Fri, 20 Sep 2019 23:04:45 +0000 Ulrich Weigand <ulrich.weigand@de.ibm.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZSchedule.td#0f0a8b77 [SystemZ] Add support for new cpu architecture - arch13This patch series adds support for the next-generation arch13CPU architecture to the SystemZ backend.This includes:- Basic support for the new processor and its features.- Assembler/disassembler support for new instructions.- CodeGen for new instructions, including new LLVM intrinsics.- Scheduler description for the new processor.- Detection of arch13 as host processor.Note: No currently available Z system supports the arch13architecture. Once new systems become available, theofficial system name will be added as supported -march name.llvm-svn: 365932 List of files: /llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZSchedule.td Fri, 12 Jul 2019 18:13:16 +0000 Ulrich Weigand <ulrich.weigand@de.ibm.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZSchedule.td#2946cd70 Update the file headers across all of the LLVM projects in the monorepoto reflect the new license.We understand that people may be surprised that we're moving the headerentirely to discuss the new license. We checked this carefully with theFoundation's lawyer and we believe this is the correct approach.Essentially, all code in the project is now made available by the LLVMproject under our new license, so you will see that the license headersinclude that license only. Some of our contributors have contributedcode under our old license, and accordingly, we have retained a copy ofour old license notice in the top-level files in each project andrepository.llvm-svn: 351636 List of files: /llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZSchedule.td Sat, 19 Jan 2019 08:50:56 +0000 Chandler Carruth <chandlerc@gmail.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZSchedule.td#f107b727 [SystemZ] Improve handling of instructions which expand to several groupsSome instructions expand to more than one decoder group.This has been hitherto ignored, but is handled with this patch.Review: Ulrich Weigandhttps://reviews.llvm.org/D50187llvm-svn: 338849 List of files: /llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZSchedule.td Fri, 03 Aug 2018 10:43:05 +0000 Jonas Paulsson <paulsson@linux.vnet.ibm.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZSchedule.td#374af807 [SystemZ] Use tablegen loops in SchedModelsNFC changes to make scheduler TableGen files more readable, by using loopsinstead of a lot of similar defs with just e.g. a latency value that changes.https://reviews.llvm.org/D49598Review: Ulrich Weigand, Javed Absharllvm-svn: 337909 List of files: /llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZSchedule.td Wed, 25 Jul 2018 11:42:55 +0000 Jonas Paulsson <paulsson@linux.vnet.ibm.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZSchedule.td#c88d3f6a [SystemZ] Reimplent SchedModel IssueWidth and WriteRes/ReadAdvance mappings.As a consequence of recent discussions(http://lists.llvm.org/pipermail/llvm-dev/2018-May/123164.html), this patchchanges the SystemZ SchedModels so that the IssueWidth is 6, which is thedecoder capacity, and NumMicroOps become the number of decoder slots neededper instruction.In addition, the SchedWrite latencies now match the MachineInstructionsdef-operand indexes, and ReadAdvances have been added on instructions withone register operand and one memory operand.Review: Ulrich Weigandhttps://reviews.llvm.org/D47008llvm-svn: 337538 List of files: /llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZSchedule.td Fri, 20 Jul 2018 09:40:43 +0000 Jonas Paulsson <paulsson@linux.vnet.ibm.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZSchedule.td#2b3482fe [SystemZ] Add support for IBM z14 processor (1/3)This patch series adds support for the IBM z14 processor. This part includes:- Basic support for the new processor and its features.- Support for new instructions (except vector 32-bit float and 128-bit float).- CodeGen for new instructions, including new LLVM intrinsics.- Scheduler description for the new processor.- Detection of z14 as host processor.Support for the new 32-bit vector float and 128-bit vector floatinstructions is provided by separate patches.llvm-svn: 308194 List of files: /llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZSchedule.td Mon, 17 Jul 2017 17:41:11 +0000 Ulrich Weigand <ulrich.weigand@de.ibm.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZSchedule.td#c7eb5a95 [SystemZ] Add decimal integer instructionsThis adds the set of decimal integer (BCD) instructions forassembler / disassembler use.llvm-svn: 302646 List of files: /llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZSchedule.td Wed, 10 May 2017 12:42:45 +0000 Ulrich Weigand <ulrich.weigand@de.ibm.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZSchedule.td#4f0509fa [SystemZ] Correct the SchedModel regarding vector unit / instructions.* Use a generic vector unit to model the issue unit more accurately.* Update some vector instructions that actually use the vector unit for more than one cycle.Review: Ulrich Weigandllvm-svn: 286112 List of files: /llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZSchedule.td Mon, 07 Nov 2016 15:45:06 +0000 Jonas Paulsson <paulsson@linux.vnet.ibm.com> http://172.16.0.5:8080/history/llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZSchedule.td#8010b631 [SystemZ] Post-RA scheduler implementationPost-RA sched strategy and scheduling instruction annotations for z196, zEC12and z13.This scheduler optimizes decoder grouping and balances processor resources(including side steering the FPd unit instructions).The SystemZHazardRecognizer keeps track of the scheduling state, which canbe dumped with -debug-only=misched.Reviers: Ulrich Weigand, Andrew Trick.https://reviews.llvm.org/D17260llvm-svn: 284704 List of files: /llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZSchedule.td Thu, 20 Oct 2016 08:27:16 +0000 Jonas Paulsson <paulsson@linux.vnet.ibm.com>