Changes in SystemZRegisterInfo.td

b006f555 - [SystemZ/z/OS] Add XPLINK 64-bit calling convention to tablegen.

Fri, 19 Feb 2021 22:44:10 +0000

[SystemZ/z/OS] Add XPLINK 64-bit calling convention to tablegen.This commit adds the initial changes to the SystemZ targetdescription for the XPLINK 64-bit calling convention on z/OS.Additions include: - a new predicate IsTargetXPLINK64 - different register allocation order - generaton of nopr after a callReviewed-by: uweigandDifferential Revision: https://reviews.llvm.org/D96887 List of files: /llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td

2cb48d62 - [TableGen] Drop deprecated leading # operation (NOP) and replace ## with #

Sat, 25 Apr 2020 22:58:40 +0000

[TableGen] Drop deprecated leading # operation (NOP) and replace ## with # List of files: /llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td

8e42f6dd - [SystemZ] Model floating-point control register

Mon, 13 May 2019 09:47:26 +0000

[SystemZ] Model floating-point control registerThis adds the FPC (floating-point control register) as a reservedphysical register and models its use by SystemZ instructions.Note that only the current rounding modes and the IEEE exceptionmasks are modeled. *Changes* of the FPC due to exceptions (inparticular the IEEE exception flags and the DXC) are not modeled.At this point, this patch is mostly NFC, but it will preventscheduling of floating-point instructions across SPFC/LFPC etc.llvm-svn: 360570 List of files: /llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td

2946cd70 - Update the file headers across all of the LLVM projects in the monorepo

Sat, 19 Jan 2019 08:50:56 +0000

Update the file headers across all of the LLVM projects in the monorepoto reflect the new license.We understand that people may be surprised that we're moving the headerentirely to discuss the new license. We checked this carefully with theFoundation's lawyer and we believe this is the correct approach.Essentially, all code in the project is now made available by the LLVMproject under our new license, so you will see that the license headersinclude that license only. Some of our contributors have contributedcode under our old license, and accordingly, we have retained a copy ofour old license notice in the top-level files in each project andrepository.llvm-svn: 351636 List of files: /llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td

2a119b9a - [SystemZ] Replace subreg_r with subreg_h

Wed, 15 Aug 2018 15:21:23 +0000

[SystemZ] Replace subreg_r with subreg_hChange subreg_r32 -> subreg_h32 subreg_r64 -> subreg_h64 subreg_hr32 -> subreg_hh32The subregisters subreg_r32 and subreg_r64 were added to emphasize thefact that modifying these subregisters may clobber the entire register.This is not necessarily the case for subreg_h32, et al.However, the ability to compose subreg_h64 with subreg_r32, and withsubreg_h32 and subreg_l32 at the same time makes the compositions betreated as non-overlapping (leading to problems when tracking subregliveness). See D50468 for more details.Differential Revision: https://reviews.llvm.org/D50725llvm-svn: 339778 List of files: /llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td

b32f3656 - [SystemZ] Do not use glue to represent condition code dependencies

Mon, 30 Apr 2018 17:52:32 +0000

[SystemZ] Do not use glue to represent condition code dependenciesCurrently, an instruction setting the condition code is linked tothe instruction using the condition code via a "glue" link in theSelectionDAG. This has a number of drawbacks; in particular, itmeans the same CC cannot be used by multiple users. It also makesit more difficult to efficiently implement SADDO et. al.This patch changes the back-end to represent CC dependencies asnormal values during SelectionDAG matching, along the lines ofhow this is handled in the X86 back-end already.In addition to the core mechanics of updating all relevant patterns,this requires a number of additional changes:- We now need to be able to spill/restore a CC value into a GPR if necessary. This means providing a copyPhysReg implementation for moves involving CC, and defining getCrossCopyRegClass.- Since we still prefer to avoid such spills, we provide an override for IsProfitableToFold to avoid creating a merged LOAD / ICMP if this would result in multiple users of the CC.- combineCCMask no longer requires a single CC user, and no longer need to be careful about preventing invalid glue/chain cycles.- emitSelect needs to be more careful in marking CC live-in to the basic block it generates. Also, we can now optimize the case of multiple subsequent selects with the same condition just like X86 does.llvm-svn: 331202 List of files: /llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td

a9f05a9d - [SystemZ] Make AnyRegBitRegClass unallocatable.

Fri, 16 Mar 2018 15:21:26 +0000

[SystemZ] Make AnyRegBitRegClass unallocatable.AnyReg is just for the assembler and it is better to have it as notallocatable in order to simplify (make more intuitive) the RegPressureSets.Review: Ulrich Weigandllvm-svn: 327715 List of files: /llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td

18f6930f - [SystemZ] Support vector registers in inline asm

Fri, 02 Mar 2018 20:36:34 +0000

[SystemZ] Support vector registers in inline asmThis adds support for specifying vector registers for use with inlineasm statements, either via the 'v' constraint or by explicit registernames (v0 ... v31).llvm-svn: 326609 List of files: /llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td

fc4f323a - [SystemZ] Add the CoveredBySubRegs bit to GPR64, GPR128 and FPR128 registers.

Tue, 12 Sep 2017 12:11:29 +0000

[SystemZ] Add the CoveredBySubRegs bit to GPR64, GPR128 and FPR128 registers.This bit is needed in order for the CalleeSavedRegs list to automaticallyinclude the super registers if all of their subregs are present.Thanks to Wei Mi for initially indicating this deficiency in the SystemZbackend.Review: Ulrich Weigand.https://bugs.llvm.org/show_bug.cgi?id=34550llvm-svn: 313023 List of files: /llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td

f2968d58 - [SystemZ] Add support for IBM z14 processor (3/3)

Mon, 17 Jul 2017 17:44:20 +0000

[SystemZ] Add support for IBM z14 processor (3/3)This adds support for the new 128-bit vector float instructions of z14.Note that these instructions actually only operate on the f128 type,since only each 128-bit vector register can hold only one 128-bitfloat value. However, this is still preferable to the legacy 128-bitfloat instructions, since those operate on pairs of floating-pointregisters (so we can hold at most 8 values in registers), while thenew instructions use single vector registers (so we hold up to 32value in registers).Adding support includes:- Enabling the instructions for the assembler/disassembler.- CodeGen for the instructions. This includes allocating the f128 type now to the VR128BitRegClass instead of FP128BitRegClass.- Scheduler description support for the instructions.Note that for a small number of operations, we have no new vectorinstructions (like integer <-> 128-bit float conversions), and sowe use the legacy instruction and then reformat the operand(i.e. copy between a pair of floating-point registers and avector register).llvm-svn: 308196 List of files: /llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td

33435c4c - [SystemZ] Add support for IBM z14 processor (2/3)

Mon, 17 Jul 2017 17:42:48 +0000

[SystemZ] Add support for IBM z14 processor (2/3)This adds support for the new 32-bit vector float instructions of z14.This includes:- Enabling the instructions for the assembler/disassembler.- CodeGen for the instructions, including new LLVM intrinsics.- Scheduler description support for the instructions.- Update to the vector cost function calculations.In general, CodeGen support for the new v4f32 instructions closelymatches support for the existing v2f64 instructions.llvm-svn: 308195 List of files: /llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td

03ab2e2b - [SystemZ] Add all remaining instructions

Fri, 30 Jun 2017 20:43:40 +0000

[SystemZ] Add all remaining instructionsThis adds all remaining instructions that were still missing, mostlyprivileged and semi-privileged system-level instructions. These areprovided for use with the assembler and disassembler only.This brings the LLVM assembler / disassembler to parity with theGNU binutils tools.llvm-svn: 306876 List of files: /llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td

fffc7110 - [SystemZ] Model access registers as LLVM registers

Tue, 08 Nov 2016 20:15:26 +0000

[SystemZ] Model access registers as LLVM registersAdd the 16 access registers as LLVM registers. This allows removinga lot of special cases in the assembler and disassembler where wewere handling access registers; this can all just use the genericregister code now.Also add a bunch of instructions to operate on access registers,for assembler/disassembler use only. No change in code generationintended.llvm-svn: 286283 List of files: /llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td

4fbc3f4a - [SystemZ] Add support for the .insn directive

Mon, 08 Aug 2016 15:13:08 +0000

[SystemZ] Add support for the .insn directiveSummary:Add support for the .insn directive..insn is an s390 specific directive that allows encoding of an instructioninstead of using a mnemonic. The motivating case is some code in node.js thatrequires support for the .insn directive.Reviewers: koriakin, uweigandSubscribers: koriakin, llvm-commitsDifferential Revision: https://reviews.llvm.org/D21809llvm-svn: 278012 List of files: /llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td

45d5c673 - [SystemZ] Make the CCRegs regclass non-allocatable.

Thu, 29 Oct 2015 16:13:55 +0000

[SystemZ] Make the CCRegs regclass non-allocatable.This was discovered to be necessary while running memchr-01.ll with-verify-machinstrs, because it is not allowed to have a phys reg liveaccross block boundaries while on SSA form, if the register isallocatable (expect in entry block and landing pads).In this test case, stringRRE pseudos are expanded after isel by addinga loop block which produces a live out CC register. To make the testpass, it was also necessary to not say that StringRRELoop pseudo usesR0L, this is only true for the StringRRE opcode.-verify-machineinstrs added to memchr-01.ll test.New test case int-cmp-51.ll to test that MachineCSE can eliminatean identical compare (which it couldn't do before).Reviewed by Ulrich Weigandllvm-svn: 251634 List of files: /llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td

a8b04e1c - [SystemZ] Add z13 vector facility and MC support

Tue, 05 May 2015 19:23:40 +0000

[SystemZ] Add z13 vector facility and MC supportThis patch adds support for the z13 processor type and its vector facility,and adds MC support for all new instructions provided by that facilily.Apart from defining the new instructions, the main changes are:- Adding VR128, VR64 and VR32 register classes.- Making FP64 a subclass of VR64 and FP32 a subclass of VR32.- Adding a D(V,B) addressing mode for scatter/gather operations- Adding 1-, 2-, and 3-bit immediate operands for some 4-bit fields. Until now all immediate operands have been the same width as the underlying field (hence the assert->return change in decode[SU]ImmOperand).In addition, sys::getHostCPUName is extended to detect running nativelyon a z13 machine.Based on a patch by Richard Sandiford.llvm-svn: 236520 List of files: /llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td

9ac2f9b2 - [SystemZ] Reclassify f32 subregs of f64 registers

Mon, 04 May 2015 17:41:22 +0000

[SystemZ] Reclassify f32 subregs of f64 registersAt the moment, all subregs defined by the SystemZ target can be modifiedindependently of the wider register. E.g. writing to a GR32 does notchange the upper 32 bits of the GR64. Writing to an FP32 does not changethe lower 32 bits of the FP64.Hoewver, the upcoming support for the vector extension redefines FP64 asone half of a V128. Floating-point operations leave the other half ofa V128 in an unpredictable state, so it's no longer the case that writingto an FP32 leaves the bits of the underlying register (the V128) alone.I'd prefer to have separate subreg_ names for this situation, so thatit's obvious at a glance whether we're talking about a subreg that leavesthe other parts of the register alone.No behavioral change intended.Patch originally by Richard Sandiford.llvm-svn: 236433 List of files: /llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td

ac1dba0f - [SystemZ] Fix FPR dwarf numbering

Thu, 10 Jul 2014 10:45:11 +0000

[SystemZ] Fix FPR dwarf numberingThe dwarf FPR numbers are supposed to have the order F0, F2, F4, F6,F1, F3, F5, F7, F8, etc., which matches the pairing of registers forlong doubles. E.g. a long double stored in F0 is paired with F2.llvm-svn: 212701 List of files: /llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td

0755c93b - [SystemZ] Use upper words of GR64s for codegen

Tue, 01 Oct 2013 11:26:28 +0000

[SystemZ] Use upper words of GR64s for codegenThis just adds the basics necessary for allocating the upper words tovirtual registers (move, load and store). The move support is parameterisedin a way that makes it easy to handle zero extensions, but the associatedzero-extend patterns are added by a later patch.The easiest way of testing this seemed to be add a new "h" registerconstraint for high words. I don't expect the constraint to be usefulin real inline asms, but it should work, so I didn't try to hide itbehind an option.llvm-svn: 191739 List of files: /llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td

f9496060 - [SystemZ] Add GRH32 for the high word of a GR64

Mon, 30 Sep 2013 10:45:16 +0000

[SystemZ] Add GRH32 for the high word of a GR64The only thing this does on its own is make the definitions of RISB[HL]Ga bit more precise. Those instructions are only used by the MC layer atthe moment, so no behavioral change is intended. The class is needed bylater patches though.llvm-svn: 191660 List of files: /llvm-project-15.0.7/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td